Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region ( 4 ) and an n-type drift region ( 3 ) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region ( 4 ) or n-type drift region ( 3 ) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions ( 4 ) and n-type drift regions ( 3 ) forming the pn-repeating structure.  
     Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained.  
     In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and amanufacturing method for the same, and more particularly to animprovement in performance and an increase in the yield of a powersemiconductor device.

BACKGROUND ART

[0002] An element using a repeating microscopic structure of p-type andn-type layers wherein an electric field relaxation phenomenon called theRESURF (REduced SURface Field) effect is applied in place of the uniformn-type drift layer of a conventional MOS-FET (Metal OxideSemiconductor-Field Effect Transistor) has been proposed in, forexample, U.S. Pat. No. 6,040,600. In this element a low ON resistance isobtained in the ON condition due to the n-type drift layer of which theimpurity concentration is higher than the concentration of the uniform ndrift layer in the conventional structure by approximately one orderwhile in the OFF condition the entire electric field is relaxed due to athree-dimensional multiple RESURF effect of n/p layers. Thereby, awithstand voltage several times as large as the main withstand voltageconventionally obtained by a high concentration single n-type driftlayer alone can be implemented and, in principle, an STM (Super Trenchpower MOS-FET) structure that can obtain a value lower than the Silimitation (Ron, sp=5.93×10⁻⁹ BV^(2.5), wherein specific resistance isproportional to the main withstand voltage to the power of 2.5) whereinthe relationship between the main withstand voltage and the specific ONresistance is limited can be obtained.

[0003] In an actual element, however, this repeating microscopicstructure of p-type and n-type layers cannot be repeated infinitely inan edge portion of the chip and, therefore, there is a problem wherein adrop in the main withstand voltage is great in a “termination” portionof a termination structure where the repetition ends. In the following,a prior art and problem thereof are described from such a point of view.

[0004]FIG. 148 is a cross sectional view schematically showing the firstconfiguration of a semiconductor device according to a prior art andshows a configuration that corresponds to a case where a MOS-FET isposited as a concrete active element structure. In reference to FIG.148, an n⁻ epitaxial layer 102 is formed on the first main surface sideof an n⁺ drain region 101 of the MOS-FET. A pn-repeating structurewherein n-type drift regions 103 and p-type impurity regions 104 arerepeated in alternation is formed within this n⁻ epitaxial layer 102.

[0005] Here, though the vicinity of the center of this element havingthe pn-repeating structure is omitted for the purpose of simplificationof the description, conventionally a combination of several hundreds toseveral tens of thousands of repeated pairs of n-type drift regions 103and p-type impurity regions 104 exists in this portion. The n-typeimpurity concentration of n-type drift region 103 and the p-typeimpurity concentration of p-type impurity region 104 in each pair areset at substantially the same level.

[0006] A p-type body region 105 is formed on the first main surface sideof p-type impurity region 104. This p-type body region 105 is alsolocated on, at least, a portion of n-type drift region 103 on the firstmain surface side so as to form a main pn junction with n-type driftregion 103. An n⁺ source region 106 of a MOS-FET and a p⁺ contact region107 for making a low resistance contact with p-type body region 105 areformed side by side in the first main surface within this p-type bodyregion 105.

[0007] A gate electrode 109 is formed above the first main surface so asto face p-type body region 105 located between n-type drift region 103and n⁺ source region 106 via a gate insulating film 108. When a positivevoltage is applied to this gate electrode 109, p-type body region 105,which faces gate electrode 109, is inverted to an n-type so that achannel region is formed.

[0008] A source electrode 110 made of a material including aluminum(Al), for example, is formed on the first main surface so as to beelectrically connected to n⁺ source region 106 and p⁺ contact region107.

[0009] A drain metal wire 111 is formed on the second main surface so asto contact n⁺ drain region 101.

[0010] Here, in the actual element, the source electrode part iselectrically connected to n⁺ source region 106 and p⁺ contact region 107through a contact hole provided in an interlayer insulating film on thefirst main surface and via a barrier metal. In the present application,however, this portion is not important and, therefore, the sourceelectrode part is simplified and expressed using solid lines throughoutall of the drawings.

[0011] In addition, though n⁺ drain region 101 is several times toseveral tens of times thicker than the effective element portion in theactual element, n⁺ drain region 101 is expressed as thinner than theeffective element portion in the drawings for the purpose ofsimplification. In addition to the above, scales, ratios of dimensions,and the like, are deformed in order to simplify the expression and,therefore, the respective dimensions in the drawings are not necessarilyprecise.

[0012] A multiple guard ring structure made of p-type impurity regions115, for example, is provided as a termination structure of thepn-repeating structure.

[0013] In this configuration, n-type drift regions 103 and p-typeimpurity regions 104, respectively, have substantially the same impurityconcentration in the center portion and edge portions of thepn-repeating structure.

[0014]FIG. 149 is a cross sectional view schematically showing thesecond configuration of the semiconductor device according to the priorart. In reference to FIG. 149, an n⁻ epitaxial layer 102 has a buriedmulti-layer epitaxial structure and a p-type impurity region 104 isformed of a plurality of p-type regions 104 a that are integrated in thedepth direction of the semiconductor substrate in this configuration. Inthis configuration, p-type impurity regions 104, respectively, have thesame impurity concentration in the center portion and edge portions ofthe pn-repeating structure.

[0015] Here, the concentration distribution in the upward and downwarddirections of each p-type impurity region 104 is an intrinsic structureand this is a concentration distribution due to the manufacturingmethod, which has no bearing on the concentration gradient in the partin the lateral direction discussed in the present invention. Inaddition, though in the drawing the concentration gradient in the upwardand downward directions is depicted in only two stages for the purposeof simplification, in practice this concentration sequentially changes.

[0016] A manufacturing method according to this prior art ischaracterized in that n⁻ epitaxial layer 102, having a comparativelyhigh concentration to the extent that the concentration thereof isbalanced with that of the p-type layers, is used for the purpose ofsimplifying the process of formation of the buried layers. A heattreatment is carried out after forming p-type buried diffusion layers104 a within n⁻ epitaxial layer 102 in such a manner and, therefore,p-type impurity region 104 becomes of a form well-known in Japan as“round sweet balls of confectionary on a skewer.”

[0017]FIG. 150 is a cross sectional view schematically showing the thirdconfiguration of the semiconductor device according to the prior art. Inreference to FIG. 150, n-type drift regions 103 and p-type impurityregions 104 form pairs and a trench 123 filled in with a filling 124 isarranged between the members of each combined pn pair in thisconfiguration.

[0018]FIG. 151 shows the appearance of electrical field concentration inthe structure corresponding to this FIG. 150. The dark portion in thisfigure indicates a portion of high electrical field concentration and itis seen that an electrical field concentrates on portions (regions shownby arrows) wherein the pn-repeating structure ends.

[0019] Here, in this FIG. 151, an FP (Field Plate) structure is adoptedfor the termination structure portions instead of the multiple guardring called an FLR (Field Limiting Ring) or an FFR (Floating FieldRing).

[0020] Here, the other parts of the above described configurations shownin FIGS. 149 and 150 are approximately the same as in the configurationshown in FIG. 148 and, therefore, the same symbols are attached to thesame members, of which the descriptions are omitted.

[0021] As described above, according to the first to third prior artsthere are structures wherein conventional termination structures such asa guard ring, an LFR, a JTE (Junction Termination Extension) and an FPare combined in the portions wherein pn-repeating structures end. Bycombining such termination structures, however, only a withstand voltagefar lower than the high withstand voltage obtained within the cell inthe center portion of the pn-repeating structures can be obtained inportions wherein the pn-repeating structure ends. Therefore, though theelement operates, there is a problem wherein the trade-off relationshipbetween the main withstand voltage and the ON resistance does notimprove.

[0022] In addition, the content of the following Prior Art 1 has beenannounced as a method for preventing the loss of the high withstandvoltage of the main cell portion by setting a specific concentration ofthe p-type layers and of the n-type layers outside of the portionswherein the pn-repeating structures ends. According to this technique,however, there is a problem wherein implementation is difficult due tothe reasons described below.

[0023] The above described Prior Art 1 is described in “JunctionTermination Technique for Super Junction Devices” that was announced in,for example, ISPSD 2000 (International Symposium on Power SemiconductorDevices & ICs) of CPES (Center for Power Electronics Systems), VirginiaPolytechnic Institute and State University.

[0024] This Prior Art 1 shows improvement of the termination structureitself in the pn-repeating structure.

[0025] In addition, the structure shown in FIG. 152 is shown in theabove described Prior Art 1. In reference to FIG. 152, a region of whichthe effective conductive type and concentration can be regarded as thoseof a low concentration p⁻ region in a fan form of a quarter of a circlehaving a radius of R of the thickness (depth) of an n layer is formedfrom a portion wherein the repetition of p layers 204 and n layers 203ends. However, a p⁻ region cannot actually be formed to have such aconcentration distribution. Therefore, it is necessary for theconcentration distribution of the effective p⁻ region to have anattenuation curve as shown in FIG. 153.

[0026] In order to implement this, a configuration is used wherein theconcentration and the width of n-type regions 203 are constant while theconcentration of p-type regions 204 is constant and the widths thereofare changed such as in the SJT (Super Junction Termination) structureshown in FIG. 154. Thereby, the same effects as of the changing of theeffective concentration can be obtained according to the description ofPrior Art 1.

[0027] In addition, the only requirements at this time are a formwherein the equipotential surfaces are aligned in fans at equalintervals as shown in FIG. 155 and a zigzag electrical field intensitydistribution that is exposed to the surface wherein the peaks and thetroughs have the same height and depth, respectively.

[0028] In addition, in this Prior Art 1 each of the concentrations ofp_(i) regions 204 and n_(i) regions 203 are posited as being uniformwithin the single diffusion layer in the upward, downward, leftward andrightward directions. There is a problem, however, wherein the originaleffects of Prior Art 1 cannot easily be exercised when the formula forthe relationship of the pn concentration ratio is not fulfilled in thecase that the absolute values of the concentration greatly change orwhen the description of such a relationship becomes extremely complex sothat the precision of proximity is reduced.

[0029] Concretely, there is a description that “along the SJT surface, .. . in the following calculation.” in right column of page 2 to the leftcolumn of page 3 in the main body of Prior Art 1. In this descriptionthe volume represented by the concentration and the width of eachportion may be set so as to satisfy equation (5) in Prior Art 1 so thatthe electrical field distribution closest to the surface does not reachto the critical breakdown electrical field.

[0030] In other words, this Prior Art 1 discloses the design of theentirety of the element in a form that includes the terminationstructure by literally extending the super junction structure of therepeating cell portions to the termination structure portions in somemanner according to SJT, that is to say, “Super Junction Terminationstructure,” wherein a repeating cell portion in the center and atermination structure have a one-to-one correspondence so as to beindivisible having a very limitative structure while “manner ofconnection” of a repeating cell portion to a general terminationstructure portion is described in the present invention, which isessentially different from the above.

[0031] In the case that the distribution required for the p-typeacceptor concentration distribution in the moving radius direction inFIG. 153 is formed according to the repetition of pn layers, theelectrical field distribution closest to the surface becomes of a zigzagform and, in the case that the peaks and troughs all have the samevalue, the maximum withstand voltage can be obtained. Therefore, in thecase that the all of the concentrations of n and p regions 203 and 204are made uniform so that the equipotential surfaces (lines) distributein fan forms at equal intervals, as shown in FIG. 155, it is necessaryto carry out an adjustment of the width of each of the regions 203 and204.

[0032] In addition, SJT is considered to be impractical because it hasthe following two problems.

[0033] First, concentration regulation for forming an SJT structure istoo complicated and it is necessary to apply an interval design thatagrees with the concentration arrangement of the repeating cell portionsthat are different from the termination structure portions to the SJTpart after examining the arrangement in detail before carrying out theactual design and, in addition, it is physically and mechanicallydifficult to fabricate a semiconductor chip structure to includeterminal edges. On the other hand, the present invention has theadvantage that both design and manufacturing method are simple becausethe relative concentrations in the vicinity of the terminal edges of therepeating cell portions may be adjusted using comparatively simplearithmetic.

[0034] Secondly, an SJT structure can only be implemented in the case ofmanufacture by means of a buried multi-layer epitaxial growth method andlacks versatility in that it cannot be actually manufactured in the casewherein a trench sidewall diffusion is used.

[0035] Furthermore, as described in the main body of Prior Art 1, thereis a problem wherein this technique lacks versatility in that it isimpossible to apply this technique in an element structure wherein atrench system is applied due to restrictions of the manufacturingtechnology even though the application to a multi-layer epitaxialstructure is, in principle, possible.

[0036] Next, the technology disclosed in U.S. Pat. No. 5,438,215 isdescribed as prior art 2 in FIG. 156.

[0037] In reference to FIG. 156, a vertical-type MOS-FET has insideregion 301 that is doped so as to be a low level n-type. A base region303 of the opposite conductive type (p) is provided in the upper sidesurface 302 of the semiconductor substrate. A source region 304 of thefirst conductive type (n) is buried within base region 303. A gateelectrode 308 is arranged above surface 302 so as to be insulated fromthe surface. A drain region 307 that is highly doped so as to be of thesame conductive type as inside region 301 is provided in the surface 306on the opposite side.

[0038] Auxiliary semiconductor regions 311 and 312 are arranged in arange of the space-charge region that spreads at the time of reversevoltage application within the inside region 301. At least two regions211 of a conductive type opposite to that of the inside region areprovided. Auxiliary regions 312 having the same the same conductive type(n) as inside region 301 and being more highly doped than the insideregion arranged between regions 311. The auxiliary regions aresurrounded from all directions by a single region. This single region isof the same conductive type as the inside region, as well as regions312, and is more highly doped than the inside region.

[0039] Though in this configuration a portion, wherein an active cell isformed, is buried in n⁻ region 301, which has a low concentration, theimpurity concentration of this outer peripheral portion is notspecifically described and only the method of formation of a cellportion is discussed.

[0040] In addition, in general the impurity concentration of a portionwherein a pn-repeating structure is not formed in this Prior Art 2 ispresumed to be set at the impurity concentration that is reversecalculated from a value obtained by adding a manufacturing margin to theelement withstand voltage set for the power MOS-FET of a conventionalstructure (structure that does not have pn repetition). However, thatleads the electrical field distribution in the termination structureportions in the pn-repeating structure to become triangular so as todiffer from an electrical field distribution in a trapezoidal form thatis implemented in the cell portion. Therefore, in the same manner as inthe above described Prior Art 1, the difference in the electrical fielddistribution between the inside of repeating cells and the terminationstructure portions becomes greater so that there is a problem wherein ahigh withstand voltage, which is essentially obtained in a cell portion,cannot be implemented although the relationship between the mainwithstanding voltage and the ON resistance is improved in comparisonwith the conventional MOS-FET structure.

DISCLOSURE OF THE INVENTION

[0041] An object of the present invention is to provide a structurewhich improves the trade-off relationship between the main withstandingvoltage and the ON resistance, and a manufacturing method capable ofimplementing such a structure in a semiconductor device based on athree-dimensional multiple RESURF effect.

[0042] A semiconductor device of the present invention is asemiconductor device having a repeating structure, wherein a structurewhere a first impurity region of a first conductive type and a secondimpurity region of a second conductive type are aligned side by side, isrepeated twice or more in a semiconductor substrate of the firstconductive type, characterized in that a low concentration region, whichis either the first or the second impurity region located at theoutermost portion in the repeating structure, has the lowest impurityconcentration or has the least generally effective charge amount fromamong all of the first and second impurity regions forming the repeatingstructure.

[0043] According to the semiconductor device of the present invention aportion of the concentration of the outermost portion in the repeatingstructure is converted to have a concentration lower than the centerportion and, thereby, the “mitigating region” that gradually mitigatesthe strong “three-dimensional multiple RESURF effect” used in therepeating cell portion in the center portion is provided so that theconnection with a conventional so-called “termination structure” portionformed of a guard ring or a field plate is made easier and the mainwithstanding voltage drop caused by “mismatch” in the connection betweenthe strong “three-dimensional multiple RESURF effect” portion and aso-called “termination structure” portion can be restricted.

[0044] In the above described semiconductor device the impurityconcentration of the low concentration region is preferably no lowerthan 30% and no higher than 70% of the impurity concentration of thehigh concentration region that is either the first or second impurityregion located closer to the center portion of the repeating structurethan is the low concentration region.

[0045] By adjusting the impurity concentration in such a manner, itbecomes possible to adjust the concentration gradient from the centerportion of the pn-repeating structure to the first conductive region ofthe semiconductor substrate to be in a range that can be regarded asbeing continuous.

[0046] In the above described semiconductor device, the impurityconcentration of the middle concentration region, which is of the abovedescribed first or second impurity region located between the lowconcentration region and the high concentration region, is higher thanthe impurity concentration of the low concentration region and is lowerthan the impurity concentration of the high concentration region.

[0047] Furthermore, by providing a the middle concentration region insuch a manner, it becomes possible to continuously change theconcentration gradient from the center portion of the pn-repeatingstructure to the first conductive region of the semiconductor substrate.

[0048] In the above described semiconductor device, the semiconductorsubstrate preferably has a first main surface and a second main surfacefacing each other wherein a third impurity region of the secondconductive type is formed in, at least, a portion of at least one of theplurality of the first impurity regions on the first main surface sidethat forms the repeating structure so as to form a main pn junctionswith the first impurity regions and a fourth impurity region of thefirst conductive type is formed on the second main surface side of therepeating structure.

[0049] Thus, the present invention can be applied to an element having avertical-type structure.

[0050] In the above described semiconductor device, the third impurityregion that forms the main pn junctions with the first impurity regionsis preferably a body region of an insulating gate-type field effecttransistor portion.

[0051] Thus, the present invention can be applied to an element having aMOS-FET.

[0052] In the above described semiconductor device, the lowconcentration regions located at the outermost portion in the repeatingstructure do not form active elements.

[0053] Thereby, the withstand voltage alone can be maintained in the lowconcentration regions having a concentration gradient that tends to beunstable at the time of switching operation without forming an element,such as a MOS-FET, so that stable switching operation can be obtained.

[0054] In the above described semiconductor device, a third impurityregion of the second conductive type formed in, at least, a portion ofthe upper portion of the first impurity region close to an end thatextends in one specific direction, a fourth impurity region of the firstconductive type formed in, at least, a portion of the upper portion ofthe first impurity region close to an end in the direction opposite tothe above described one specific direction, a first electrodeelectrically connected to the third impurity region and a secondelectrode electrically connected to a fourth impurity region are furtherprovided, wherein the first and second electrodes are both formed on thefirst main surface.

[0055] Thus, the present invention can be applied to an element having alateral-type structure.

[0056] In the above described semiconductor device, the semiconductorsubstrate preferably has a first main surface and a second main surfacethat face each other and has a plurality of trenches in the first mainsurface, wherein the repeating structure has a structure where astructure in which the first and second impurity regions are arrangedside by side with a trench located in between is repeated twice or more.

[0057] Thus, the present invention can be applied to an element having atrench, for example, an ST (Super Trench) type element.

[0058] In the above described semiconductor device, the impurityconcentration of the low concentration region is preferably no lowerthan 30% and no higher than 70% of the impurity concentration of thehigh concentration region, which is the first or second impurity region,that is located closer to the center portion of the repeating structurethan is the low concentration region.

[0059] By adjusting the impurity concentration in an element having atrench in such a manner, it becomes possible to adjust the concentrationgradient from the center portion of the pn-repeating structure to thefirst conductive type region of the semiconductor substrate to be in arange such that the concentration gradient can be regarded as beingcontinuous.

[0060] In the above described semiconductor device, the impurityconcentration of the middle concentration region, which is either thefirst or the second impurity region, located between the lowconcentration region and the high concentration region is preferablyhigher than the impurity concentration of the low concentration regionand lower than the impurity concentration of the high concentrationregion.

[0061] Furthermore, by providing the middle concentration region in anelement having a trench in the above described manner, it becomespossible to continuously change the concentration gradient from thecenter portion of the pn-repeating structure to the first conductivetype region of the semiconductor substrate.

[0062] In the above described semiconductor device, a first impurityregion is formed on one side of a mesa portion of a semiconductor devicesurrounded by a plurality of trenches and a second impurity region isformed in the surface of the other side and a third impurity region ofthe second conductive type is formed in, at least, a portion of theabove described first main surface side of the first impurity region sothat the first impurity region and the main pn junction are formed.

[0063] Thus, the present invention can be applied to an element havingan ST-type mesa region.

[0064] In the above described semiconductor device, the third impurityregion forming a pn junction primarily with the first impurity region isa body region of an insulating gate-type field effect transistorportion.

[0065] Thus, the present invention can be applied to an ST-type elementhaving a MOS-FET, that is to say, to an STM (Super Trench powerMOS-FET).

[0066] In the above described semiconductor device, the lowconcentration region located at the outermost portion of the repeatingstructure preferably does not form a passive element.

[0067] Thereby, withstand voltage alone can be maintained in the ST-typeelement without forming an element, such as a MOS-FET, in a lowconcentration region having a concentration gradient which easilybecomes unstable at the time of switching operation so that a stableswitching operation can be obtained.

[0068] In the above described semiconductor device, the trenchpositioned at the outermost part of the plurality of trenches is a firsttrench in a dotted line form having a surface pattern in a dotted lineform wherein a plurality of first holes are arranged at intervals in apredetermined direction in the first main surface and the lowconcentration region is formed so as to be located along one of thesidewalls of the first trench of a dotted line form.

[0069] Thus, the present invention can be applied to an element having atrench in a dotted line form, that is to say, to an element having a DLT(Dotted Line Trench) so that the manufacturing process can besimplified.

[0070] The total of the length of the sidewalls on one side of the firstmain surface of a plurality of first holes forming the first trench of adotted line form is preferably no lower than 30% and no more than 70% ofthe length of the sidewalls on one side in the first main surface of thetrench continuously extending along a location closer to the centerportion than the first trench of a dotted line form.

[0071] Thus, in an element having the DLT structure, the length and theintervals of the holes of the trench of the dotted line form areadjusted and, thereby, the impurity concentration of the lowconcentration region can be adjusted. Thereby, it becomes possible toadjust the concentration gradient from the center portion of thepn-repeating structure to the first conductive type region of thesemiconductor substrate to be in a range that can be regarded ascontinuous.

[0072] In the above described semiconductor device, the trench locatedbetween the first trench of a dotted line form and the continuouslyextending trench is preferably a second trench of a dotted line formhaving a surface pattern in a dotted line form wherein a plurality ofsecond holes are arranged at intervals in a predetermined direction inthe first main surface and the sum of length of the sidewalls on oneside in the first main surface of the plurality of second holes thatform the second trench of a dotted line form is greater than the sum oflength of the sidewalls on one side in the first main surface of theplurality of first holes that form the first trench of a dotted lineform and is less than the length of the sidewall on one side in thefirst main surface of the continuously extending trench in the locationcloser to the center portion than the second trench of a dotted lineform.

[0073] Thus, the trenches of dotted line forms are provided in astep-by-step manner in the element having the DLT structure and,thereby, the concentration gradient can be regarded as being continuousfrom the center portion of the pn-repeating structure to the firstconductive type region of the semiconductor substrate.

[0074] In the above described semiconductor device, the first impurityregion is preferably formed on one of the sides of the mesa portion ofthe semiconductor device surrounded by a plurality of trenches and thesecond impurity region is formed on the other of the sides and the thirdimpurity region of the second conductive type is formed in, at least, aportion on the first main surface side of the first impurity region soas to form a main pn junction with the first impurity region.

[0075] Thus, the present invention can be applied to an element having aDLT structure and having an ST-type mesa region.

[0076] In the above described semiconductor device, the third impurityregion, which forms the main pn junction with the first impurity region,is a body region of an insulating gate-type field effect transistorportion

[0077] Thus, the present invention can be applied to an element having aMOS-FET in an ST-type type element having a DLT structure, that is tosay, to an STM (Super Trench power MOS-FET).

[0078] In the above described semiconductor device, the lowconcentration region located at the outermost portion of the repeatingstructure preferably does not form an active element.

[0079] Thereby, the withstand voltage alone can be maintained withoutforming an element, such as a MOS-FET, in the low concentration regionhaving a concentration gradient that tends to become unstable at thetime of switching operation in an ST-type element having a DLT structureso that a stable switching operation can be obtained.

[0080] In the above described semiconductor device, the semiconductorsubstrate preferably has a first main surface and a second main surfacefacing each other and has a plurality of trenches including first andsecond trenches adjoining each other in the first main surface wherein astructure where a first impurity region is formed in each of the twosidewalls of the first trench and a second impurity region is formed ineach of the two sidewalls of the second trench is repeated twice ormore.

[0081] Thus, the present invention can be applied to an element having atwin trench structure.

[0082] In the above described semiconductor device, the impurityconcentration of the low concentration region is no lower than 30% andno higher than 70% of the impurity concentration of the highconcentration region that is either the first or second impurity regionlocated closer to the center portion in the repeating structure than thelow concentration region.

[0083] Thus, in an element having a twin trench structure, it becomespossible to adjust the impurity concentration of the low concentrationregion and, thereby, to adjust the concentration gradient from thecenter portion in the pn-repeating structure to the first conductivetype region of the semiconductor substrate to be in a range that isregarded as being continuous.

[0084] In the above described semiconductor device, the impurityconcentration of the middle concentration region, which is either thefirst or second impurity region, located between the low concentrationregion and the high concentration region is preferably higher than theimpurity concentration of the low concentration region and is lower thanthe impurity concentration of the high concentration region.

[0085] Thus, trenches of dotted line forms are provided in a side byside manner in an element having a twin trench structure and, thereby,the concentration gradient from the center portion of the pn-repeatingstructure to the first conductive type region of the semiconductorsubstrate can be regarded as being continuous.

[0086] In the above described semiconductor device, a first impurityregion is preferably formed on one side of the mesa portion of thesemiconductor substrate surrounded by a plurality of trenches, a secondimpurity region is formed on the other side and a third impurity regionof the second conductive type is formed on, at least, a portion of thefirst main surface side of the first impurity region so as to form amain pn junction with the first impurity region.

[0087] Thus, the present invention can be applied to an element havingtwin trench structure.

[0088] In the above described semiconductor device, the third impurityregion forming the main pn junction with the first impurity region ispreferably a body region of an insulating gate-type field effecttransistor portion.

[0089] Thus, the present invention can be applied to an element having aMOS-FET in an element having a twin trench structure.

[0090] In the above described semiconductor device, the lowconcentration region located at the outermost portion of the repeatingstructure preferably does not form an active element.

[0091] Thereby, withstand voltage alone can be maintained withoutforming an element, such as a MOS-FET, in the low concentration regionhaving a concentration gradient that tends to become unstable at thetime of switching operation in an element having a twin trench structureso that a stable switching operation can be obtained.

[0092] In the above described semiconductor device, the trench locatedat the outermost portion of the plurality of trenches is the firsttrench of a dotted line form having a surface pattern of a dotted lineform wherein a plurality of first holes are arranged at intervals in apredetermined direction in the first main surface and the lowconcentration region is formed so as to be located on one of thesidewalls of the first trench of a dotted line form.

[0093] Thus, the present invention can be applied to an element having atwin trench structure and having a DLT structure so that themanufacturing process can be simplified.

[0094] In the above described semiconductor device, the sum of thelengths of the sidewalls on one side in the first main surface of theplurality of first holes forming the first trench of a dotted line formis no greater than 30% and no less than 70% of the length of thesidewall on one side in the first main surface of the trench thatextends continuously in a location closer to the center portion than thefirst trench of a dotted line form.

[0095] Thus, in an element having a twin trench structure and having aDLT structure, by adjusting the length and intervals of the holes of thetrench of a dotted line form, the impurity concentration of the lowconcentration region can be adjusted. Thereby, it becomes possible toadjust the concentration gradient from the center portion of thepn-repeating structure to the first conductive region of thesemiconductor device to be in a range that is regarded as beingcontinuous.

[0096] In the above described semiconductor device, a trench locatedbetween the first trench of a dotted line form and the continuouslyextending trench is a second trench of a dotted line form having asurface pattern of a dotted line form wherein a plurality of secondholes are arranged at intervals in a predetermined direction in thefirst main surface and the sum of the lengths of the sidewalls on oneside of the plurality of second holes forming the second trench of adotted line form in the first main surface is greater than the sum ofthe lengths of the sidewalls on one side of the plurality of first holesforming the first trench of a dotted line form and is smaller than thelength of the sidewall on one side of the continuously extending trenchthat is closer to the center portion than the second trench of a dottedline form in the above described first main surface.

[0097] Thus, by providing trenches of a dotted line form in astep-by-step manner in the element having a twin trench structure andhaving a DLT structure, the concentration gradient from the centerportion of the pn-repeating structure to the first conductive typeregion of the semiconductor substrate can be regarded as beingcontinuous.

[0098] In the above described semiconductor device, a first impurityregion is preferably formed on one side of the mesa portion of thesemiconductor substrate surrounded by the plurality of trenches, asecond impurity region is formed on the opposite side of the mesaportion and a third impurity region of the second conductive type isformed in, at least, a portion on the above described first main surfaceside of the first impurity region so as to form a main pn junction withthe first impurity region.

[0099] Thus, the present invention has a twin trench structure and a DLTstructure and can be applied to an element having an ST-type mesaregion.

[0100] In the above described semiconductor device, the third impurityregion forming a main pn junction with the first impurity region ispreferably a body region of an insulating gate-type field effecttransistor portion.

[0101] Thus, the present invention can be applied to an element having aMOS-FET in an element having a twin trench structure and a DLTstructure.

[0102] In the above described semiconductor device, the lowconcentration region located at the outermost portion of the repeatingstructure preferably does not form an active element.

[0103] Thereby, the withstand voltage alone can be maintained withoutforming an element, such as a MOS-FET, in the low concentration regionhaving a concentration gradient that tends to become unstable at thetime of switching operation in an ST-type element having a twin trenchstructure and a DLT structure so that a stable switching operation canbe obtained.

[0104] A manufacturing method for a semiconductor device of the presentinvention is characterized in that the low concentration region andother first and second impurity regions are formed by independentlychanging the concentration so that the low concentration region, whichis either the first or second impurity region located at the outermostportion of the repeating structure, has the lowest impurityconcentration or has the least generally effective charge amount fromamong all of the first and second impurity regions forming the repeatingstructure in a manufacturing method for a semiconductor device having arepeating structure wherein a structure where a first impurity region ofa first conductive type and a second impurity region of a secondconductive type are aligned side by side is repeated twice, or more, ina semiconductor substrate of the first conductive type

[0105] According to the manufacturing method for a semiconductor deviceof the present invention, the outermost portion of the repeatingstructure has a concentration lower than that of the center portion and,thereby, the concentration of i layer of a pin diode formed of therepeating structure and the region of the first conductive type of thesemiconductor substrate can be lowered. Thereby, it becomes possible toadjust the concentration of the i layer so that the withstand voltageobtained at the outermost portion of the repeating structure becomesgreater than the withstand voltage obtained in the center portion.Therefore, an increase in the withstand voltage at a cell portion can beachieved, in contrast to the prior art.

[0106] In the above described manufacturing method for a semiconductordevice, the low concentration region and other first and second impurityregions are preferably formed by means of ion implantation and heattreatment in order to independently control the concentration so as toform the low concentration region and other first and second impurityregions of which the concentrations have been independently changed.

[0107] Because of the formation using ion implantation in such a manner,the process can be simplified and the low concentration region can beformed under effective control. In addition, this method is suitable fora manufacturing method for a low withstand voltage element.

[0108] In the above described manufacturing method for a semiconductordevice, the low concentration region and other first and second impurityregions are preferably formed by means of ion implantation andmulti-stage epitaxial growth in order to independently control theconcentration so as to form the low concentration region and other firstand second impurity regions of which the concentrations have beenindependently changed.

[0109] Since multi-stage epitaxial growth is used, epitaxial layers can,in principle, be layered infinitely. Accordingly, this method issuitable for a manufacturing method for high withstand voltage element.

[0110] In the above described manufacturing method for a semiconductordevice, the low concentration region and other first and second impurityregions are favorably formed by independently changing theconcentrations and, therefore, the above described low concentrationregion and other first and second impurity regions have independentlychanged concentrations and are formed by means of ion implantationwherein implantation energy is changed according to multi-stages.

[0111] Since, a multi-stage ion implantation is used, the process can besimplified and the low concentration region can be formed undereffective control. In addition, this method is suitable for amanufacturing method for a low withstand voltage element.

[0112] In the above described manufacturing method for a semiconductordevice, impurity ions injected from the first openings in a mask for ionimplantation preferably form the first and second impurity regions,other than the low concentration region, while impurity ions injectedfrom the second openings, of which the total area of the openings issmaller than that of the first openings, form the low concentrationregion in order to independently change the concentrations at the timeof the formation of the low concentration region and other first andsecond impurity regions.

[0113] Thus, openings, of which the areas of the openings differ, areused and, thereby, high concentration regions are low concentrationregions can be formed at the same time through a single ion implantationprocess so that simplification of the process can be achieved.

[0114] In the above described manufacturing method for a semiconductordevice, the second openings preferably have a configuration wherein aplurality of microscopic openings separated from each other are denselyarranged so that impurity ions injected from each of the plurality ofmicroscopic openings are integrated by applying a heat treatment so asto form a finished low concentration region of which the averageimpurity concentration is lower than that of the other first and secondimpurity regions.

[0115] Thus by using the configuration wherein a plurality ofmicroscopic openings separated from each other are densely arranged, theopenings, of which the areas of the openings differ, can easily beformed.

[0116] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of creating one, ormore, trenches and a trench of a dotted line form having a surfacepattern of a dotted line form in the first main surface at the same timeby arranging the trench of a dotted line form so as to be located alongthe outside of the above one, or more, trenches wherein a plurality offirst holes are arranged at intervals in a predetermined direction andthe step of forming a low concentration region on the one sidewall ofthe trench of a dotted line form and the other first and second impurityregions on one of the sidewalls of the above one, or more, trenches atthe same time by simultaneously implanting ions in the above one, ormore, trenches and in one of sidewalls of respective trenches of adotted line form.

[0117] Thus, the trenches of a dotted line form are used in the STMstructure and, thereby, a high concentration region and a lowconcentration region can be simultaneously formed by means of a singleion implantation step so that simplification of the process can beachieved.

[0118] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of creating two, ormore, trenches in the first main surface of the semiconductor substrate,the step of implantation of impurities in order to form the first andsecond impurity regions and the step of forming a low concentrationregion by substantially lowering the concentration of the impuritiesthat have already been implanted through the ion implantation ofimpurities of a conductive type opposite to the already implantedimpurities in the one sidewall of the trench located at the outermostportion.

[0119] Thus, in the STM structure the concentration of the impurityregion at the outermost portion in the repeating structure can belowered by means of counter doping.

[0120] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of creating one, ormore, trenches in the first main surface of the semiconductor substrate,the step of ion implantation with a first implantation amount in orderto form first or second impurity regions on one side of the respectivesidewalls of the above one, or more, trenches, the step of creating anew trench at the outermost portion outside of the above one, or more,trenches in the condition wherein each of the above one, or more,trenches is filled in with a filling layer and the step of ionimplantation with a second implantation amount smaller than the firstimplantation amount in order to form a low concentration region on onesidewall of the trench at the outermost portion.

[0121] Thus, the trenches in the center portion and at the outermostportion in the pn-repeating structure can be separately created and ionimplantations can be separately implemented in the STM structure.

[0122] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of simultaneouslycreating two, or more, trenches including first and second trenchesadjoining each other in the first main surface of the semiconductorsubstrate and a trench of a dotted line form that is located along theoutside of the two, or more, trenches wherein the plurality of firstholes are arranged at intervals in a predetermined direction and that,thereby, has a surface pattern of a dotted line form in the first mainsurface, the step of ion implantation of the first impurities in orderto form the first impurity region in each of the two sidewalls of thefirst trench and the step of ion implantation of the second impuritiesin order to form the second impurity region in each of the two sidewallsof the second trench, wherein the low concentration region is formed onboth sidewalls of the trench of a dotted line form by means of animplantation at the same time as the ion implantation of the first orsecond impurities.

[0123] Thus, a trench of a dotted line form is used in a twin trenchstructure and, thereby, a high concentration region and a lowconcentration region can be simultaneously formed by means of a singleion implantation step so that simplification of the process can beachieved.

[0124] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of creating a firstgroup of trenches made of a plurality of first trenches in the firstmain surface of the semiconductor substrate, the step of ionimplantation for forming the first impurity regions in the sidewalls onboth sides of each of the first trenches, the step of creating a secondgroup of trenches made of a plurality of second trenches in the firstmain surface so that the first trenches and the second trenches arelocated in an alternating manner, the step of ion implantation forforming the second impurity regions in the sidewalls on both sides ofeach of the second trenches and the step of the implantation ofimpurities of a conductive type opposite to that of the alreadyimplanted impurities into the sidewalls on both sides of the abovedescribed trench positioned at the outermost portion under the conditionwherein the first and second trenches arranged in an alternating manner,except the trench located at the outermost portion, are filled in with afilling layer so as to substantially lower the concentration of thealready implanted impurities so that the low concentration region isformed.

[0125] Thus, in the twin trench structure, the concentration of theimpurities at the outermost portion of the repeating structure can belowered by means of counter doping.

[0126] The above described manufacturing method for a semiconductordevice is preferably provided with the step of creating a first trenchgroup made of a plurality of first trenches in the first main surface ofthe above described semiconductor substrate, the step of ionimplantation for forming the first impurity regions in the sidewalls onboth sides of each of the first trenches, the step of creating a secondgroup of trenches made of a plurality of second trenches in the firstmain surface under the condition wherein each of the first trenches isfilled in with a filling layer so that the first trenches and the secondtrenches are located in an alternating manner, the step of ionimplantation for forming the second impurity regions in the sidewalls onboth sides of each of the second trenches, the step of creating a newtrench at the outermost portion outside of the trench located at theoutermost portion of the first and second trenches arranged in analternating manner under the condition wherein each of the first andsecond trenches is filled in with a filling layer and the step offorming a low concentration region of which the impurity concentrationis lower than that of the first or second impurity region by implantingimpurity ions of the first or second conductive type.

[0127] Thus, in the twin trench structure, the trenches of the centerportion and of the outermost portion in the repeating structure can beseparately fabricated and ion implantations can also be separatelycarried out.

[0128] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of simultaneouslycreating a first group of trenches made of a plurality of first trenchesand a second group of trenches made of a plurality of second trenches inthe first main surface of the semiconductor substrate so that the firsttrenches and the second trenches are located in an alternating manner,the step of ion implantation for forming the first impurity regions inthe sidewalls on both sides of each of the plurality of first trenchesforming the first group of trenches under the condition wherein thesecond group of trenches is filled in with a first filling layer, thestep of ion implantation for forming the second impurity regions in thesidewalls on both sides of each of the plurality of second trenchesforming the second group of trenches under the condition wherein thefirst group of trenches is filled in with a second filling layer and thestep of implanting impurity ions of a conductive type opposite to thealready implanted impurities into the sidewalls on both sides of thetrench at the outermost portion under the condition wherein all of thetrenches of the plurality of first trenches forming the first group oftrenches and plurality of second trenches forming the second group oftrenches, except the trench at the outermost portion, located at theoutermost portion, are filled in with a third filling layer so as tolower the concentration of the already implanted impurities so that thelow concentration region is formed.

[0129] Thus, in the bi-pitch implantation, the concentration of theimpurity region of the outermost portion in the repeating structure canbe lowered by means of counter doping.

[0130] The above described manufacturing method for a semiconductordevice is preferably provided with the step of simultaneously creating afirst group of trenches made of a plurality of first trenches and asecond group of trenches made of a plurality of second trenches in thefirst main surface to semiconductor substrate so that the first trenchesand the second trenches are located in an alternating manner, the stepof ion implantation for forming the first impurity regions in thesidewalls on both sides of each of the plurality of first trenchesforming the first group of trenches under the condition wherein thesecond group of trenches is filled in with a first filling layer and thestep of ion implantation for forming the second impurity regions in thesidewalls on both sides of each of the plurality of second trenchesforming the second group of trenches under the condition wherein thefirst group of trenches is filled in with a second filling layer,wherein the trench at the outermost portion, located at the outermostportion, from among the trenches of the plurality of first trenchesforming the first group of trenches and the plurality of second trenchesforming the second group of trenches is a trench of a dotted line formhaving a surface pattern of a dotted line form wherein a plurality ofholes are arranged at intervals in a predetermined direction in thefirst main surface.

[0131] Thus, in the case that a bi-pitch implantation is used, a highconcentration region and a low concentration region can besimultaneously formed through a single ion implantation step by using atrench of a dotted line form and, thereby, simplification of the processcan be achieved.

[0132] The above described manufacturing method for a semiconductordevice is preferably provided with the step of forming two, or more,trenches in the first main surface of the semiconductor substrate, thestep of ion implantation of impurities for forming the first or secondimpurity regions in the sidewalls on one side of the two, or more,trenches and the step of ion implantation of impurities of the sameconductive type as that of the already implanted impurities into thesidewalls on one side of the trenches, other than the trench located atthe outermost portion, under the condition wherein the trench located atthe outermost portion, from among the two, or more, trenches, is filledin with a filling layer so as to substantially increase theconcentration of the already implanted impurities and, thereby, theabove described first or second impurity regions in the sidewalls of thetrench located at the outermost portion becomes a region of acomparatively low concentration.

[0133] Thus, in the STM structure, ion implantation of impurities of thesame conductive type is again carried out in the sidewalls of thetrenches of the center portion and, thereby, the impurity concentrationof the center portion is enhanced so that the concentration of theimpurity regions at the outermost portion of the repeating structure canbe made to be of a comparatively low concentration.

[0134] The above described manufacturing method for a semiconductordevice is preferably further provided with the step of creating a firstgroup of trenches made of a plurality of first trenches in the firstmain surface of the semiconductor substrate, the step of ionimplantation for forming the first impurity regions in the sidewalls onboth sides of each of the first trenches, the step of forming a secondgroup of trenches made of a plurality of second trenches in first mainsurface so that the first trenches and the second trenches are locatedin an alternating manner, the step of ion implantation for forming thesecond impurity regions in the sidewalls on both sides of each of thesecond trenches and the step of implanting impurities of the sameconductive type as the already implanted impurities in the sidewalls onboth sides of the trenches, other than the trench located at theoutermost portion, under the condition wherein the trench located at theoutermost portion, from among the first and second trenches arranged inan alternating manner is filled in with a filling layer so as tosubstantially increase the concentration of the already implantedimpurities so that the first or second impurity regions in the sidewallsof the trench located at the outermost portion becomes a region of acomparatively low concentration.

[0135] Thus, in the twin trench structure, ion implantation ofimpurities of the same conductive type is again carried out in thesidewalls of the center portion and, thereby, the impurity concentrationof the center portion is enhanced so that the concentration of theimpurity region at the outermost portion of the repeating structure canbe lowered to have a comparatively low concentration.

[0136] The above described manufacturing method for a semiconductordevice preferably is further provided with the step of simultaneouslycreating a first group of trenches made of a plurality of first trenchesand a second group of trenches made of a plurality of second trenches inthe first main surface of the semiconductor substrate so that the firsttrenches and second trenches are located in an alternating manner, thestep of ion implantation for forming the first impurity regions in thesidewalls on both sides of each of the plurality of first trenchesforming the first group of trenches under the condition wherein thesecond group of trenches is filled in with a first filling layer, thestep of ion implantation for forming the second impurity regions in thesidewalls on both sides of each of the plurality of second trenchesforming the second group of trenches under the condition wherein thefirst group of trenches is filled in with a second filling layer and thestep of implanting impurity ions of the same conductive type as that ofthe already implanted impurities in the sidewalls on both sides of thetrenches other than the trench at the outermost portion under thecondition wherein the trench at the outermost portion, located at theoutermost portion, from among the plurality of first trenches formingthe first group of trenches and the plurality of second trenches formingthe second group of trenches is filled in with a third filling layer soas to enhance the concentration of the already implanted impurities sothat the first or second impurity regions in the sidewalls of the trenchat the outermost portion become regions of a comparatively lowconcentration.

[0137] Thus, in the bi-pitch implantation, ion implantation ofimpurities of the same conductive type is again carried out in thesidewalls of the trenches in the center portion and, thereby, theimpurity concentration of the center portion is enhanced so that theimpurity region at the outermost portion of the repeating structure canbe made to have a comparatively low concentration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0138]FIG. 1 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the firstembodiment of the present invention;

[0139]FIG. 2 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the secondembodiment of the present invention;

[0140]FIG. 3 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirdembodiment of the present invention;

[0141]FIG. 4 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the fourthembodiment of the present invention;

[0142]FIG. 5 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the fifthembodiment of the present invention;

[0143]FIG. 6 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the sixthembodiment of the present invention;

[0144]FIG. 7 is a cross sectional view schematically showing a buriedmulti-layer epitaxial structure according to a prior art;

[0145]FIG. 8 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the seventhembodiment of the present invention;

[0146]FIG. 9 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the eighthembodiment of the present invention;

[0147]FIG. 10 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the ninthembodiment of the present invention;

[0148]FIG. 11 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the tenthembodiment of the present invention;

[0149]FIG. 12 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the eleventhembodiment of the present invention;

[0150]FIG. 13 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the twelfthembodiment of the present invention;

[0151]FIG. 14 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirteenthembodiment of the present invention;

[0152]FIG. 15 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the fourteenthembodiment of the present invention;

[0153]FIG. 16 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the fifteenthembodiment of the present invention;

[0154]FIG. 17 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the sixteenthembodiment of the present invention;

[0155] FIGS. 18 to 25 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the seventeenth embodiment of the present invention;

[0156] FIGS. 26 to 32 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the eighteenth embodiment of the present invention;

[0157] FIGS. 33 to 42 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the nineteenth embodiment of the present invention;

[0158] FIGS. 43 to 53 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twentieth embodiment of the present invention;

[0159] FIGS. 54 to 62 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-first embodiment of the present invention;

[0160]FIGS. 63 and 64 are enlarged cross sectional views of a portionshowing a portion of FIG. 55 that is shown enlarged;

[0161] FIGS. 65 to 69 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps in the case that an embodiment of the present invention has atrench;

[0162] FIGS. 70 to 78 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-second embodiment of the presentinvention;

[0163] FIGS. 79 to 86 are schematic cross sectional views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-third embodiment of the present invention;

[0164]FIGS. 87 and 88 are a cross sectional view and a perspective viewschematically showing the configuration of a semiconductor deviceaccording to the twenty-fourth embodiment of the present invention;

[0165] FIGS. 89 to 91 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-fourth embodiment of the presentinvention;

[0166]FIGS. 92 and 93 are a cross sectional view and a perspective viewschematically showing the configuration of a semiconductor deviceaccording to the twenty-fifth embodiment of the present invention;

[0167]FIGS. 94 and 95 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-sixth embodiment of the present invention;

[0168]FIG. 96 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the twenty-seventhembodiment of the present invention;

[0169] FIGS. 97 to 105 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the twenty-seventh embodiment of the presentinvention;

[0170] FIGS. 106 to 115 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to twenty-eighth embodiment of the present invention;

[0171]FIG. 116 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the twenty-ninthembodiment of the present invention;

[0172]FIG. 117 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirtiethembodiment of the present invention;

[0173]FIG. 118 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirty-firstembodiment of the present invention;

[0174]FIG. 119 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirty-secondembodiment of the present invention;

[0175] FIGS. 120 to 128 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the thirty-fourth embodiment of the presentinvention;

[0176] FIGS. 129 to 136 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the thirty-sixth embodiment of the present invention;

[0177] FIGS. 137 to 140 are schematic perspective views showing amanufacturing method for a semiconductor device in the order of thesteps according to the thirty-seventh embodiment, of the presentinvention;

[0178]FIG. 141 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirty-eighthembodiment of the present invention;

[0179]FIG. 142 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the thirty-ninthembodiment of the present invention;

[0180]FIG. 143 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the fortiethembodiment of the present invention;

[0181]FIG. 144 is a cross sectional view schematically showing theconfiguration of a semiconductor device according to the forty-firstembodiment of the present invention;

[0182]FIG. 145 is a view showing a cross section of the pn-repeatingstructure in the configuration of FIG. 144;

[0183]FIG. 146 is a perspective view schematically showing theconfiguration wherein trenches are provided in the pn-repeatingstructure in the configuration of FIG. 144;

[0184]FIG. 147 is a view showing a cross section of the pn-repeatingstructure in the configuration of FIG. 146;

[0185]FIG. 148 is a cross sectional view schematically showing the firstconfiguration of a semiconductor device according to a prior art;

[0186]FIG. 149 is a cross sectional view schematically showing thesecond configuration of a semiconductor device according to a prior art;

[0187]FIG. 150 is a cross sectional view schematically showing the thirdconfiguration of a semiconductor device according to a prior art;

[0188]FIG. 151 is a view showing the appearance of electrical fieldconcentration at the termination portions of the repetition according toa device simulation that corresponds to the prior art of FIG. 150;

[0189]FIG. 152 is a cross sectional view schematically showing theconfiguration of the semiconductor device disclosed as Prior Art 1;

[0190]FIG. 153 is a graph showing the distribution of the p-typeacceptor concentration of the moving radius of Prior Art 1;

[0191]FIG. 154 is a cross sectional view schematically showing thepn-repeating structure of the semiconductor device disclosed as PriorArt 1;

[0192]FIG. 155 is a cross sectional view showing the configuration,together with lines of potential, of the semiconductor device disclosedas Prior Art 1; and

[0193]FIG. 156 is a cross sectional view schematically showing theconfiguration of a semiconductor device disclosed in U.S. Pat. No.5,438,215.

BEST MODE FOR CARRYING OUT THE INVENTION

[0194] In order to simplify the explanation, an example of the casewherein a vertical-type MOS-FET is formed as an embodiment is cited anddescribed below. In the drawings, portions to which the samealphanumeric, or other, symbols are attached indicate the same regionsor regions having the same operation or function and a portion to whichthe same number with an alphanumeric subscript is attached indicates aportion having a similar operation or function to a region having thesame number without the alphanumeric subscript.

[0195] (Analysis in the Embodiments of the Present Specification)

[0196] Though no drawings corresponding to the analysis in theembodiments of the present specification are specifically described,this analysis is applied to all of the embodiments shown below.

[0197] That is to say, the impurity concentration of the impurity regionlocated at the outermost portion of the pn-repeating structure of ann-type impurity region 3 and a p-type impurity region 4 is set at a lowconcentration to the extent that the structure can generally be regardedas a pin diode structure. Thereby, the impurity concentration of theimpurity region located at the outermost portion of the pn-repeatingstructure has the lowest impurity concentration from among all of theimpurity regions forming the pn-repeating structure.

[0198] In addition, the impurity concentration of n⁻ epitaxial layer 2is generally set at a concentration that is lower, by approximately oneorder, than a conventional element having the same grade of mainwithstanding voltage. Thereby, a pin diode can be formed so that anapproximately trapezoidal electrical field intensity distribution formcan be obtained, in contrast to the case of a p⁺/n⁻ junction alonehaving a triangular electrical field intensity distribution. Therefore,the thickness of n⁻ epitaxial layer 2 can be made to be approximatelyhalf of that of a conventional element having the same grade of mainwithstanding voltage.

[0199] On the other hand, the withstand voltage of the cell portiondiffers from that of the case of a conventional MOS-FET structure andhas a value obtained by the multiplication of a×2×10⁵ V/cm by thethickness of n epitaxial layer 1. Here, the constant a is a number thatis experimentally found and is a number of from approximately 0.6 to1.2.

[0200] (First Embodiment)

[0201]FIG. 1 shows a configuration that corresponds to the case whereina MOS-FET is posited as a concrete active element structure. Inreference to FIG. 1, an n⁻ epitaxial layer 2 is formed on the first mainsurface side of an n⁺ drain region 1 of the MOS-FET. A pn-repeatingstructure is formed within this n⁻ epitaxial layer 2 wherein n-typedrift regions 3 and p-type impurity regions 4 are repeated inalternation.

[0202] Here, the vicinity of the center of the element having thispn-repeating structure is omitted for simplification of explanation andthe pitch of pn repetition is approximately 1 μm to 20 μm and,therefore, several hundreds to several tens of thousands of pairs ofn-type drift regions 3 and p-type impurity regions 4 usually exist inthe form of repeated combinations in this portion. The n-type impurityconcentration of an n-type drift region 3 and the p-type impurityconcentration of a p-type impurity region 4, which are combined in apair, are set at substantially the same level.

[0203] A p-type body region 5 is formed on the first main surface sideof a p-type impurity region 4. This p-type body region 5 is located in,at least, a portion of an n-type drift region 3 on the first mainsurface side so as to form a main pn junction with n-type drift region3. An n⁺ source region 6 of a MOS-FET and a p⁺ contact region 7 formaking a low resistance contact with this p-type body region 5 areformed side by side in the first main surface within this p-type bodyregion 5.

[0204] A gate electrode 9 is formed above the first main surface so asto face p-type body region 5 located between n-type drift region 3 andn⁺ source region 6 via a gate insulating film 8. When a positive voltageis applied to this gate electrode 9, p-type body region 5 facing gateelectrode 9 is inverted to an n-type so that a channel region is formed.Gate insulating film 8 is made of, for example, a silicon oxide film andgate electrode 9 is made of, for example, a polycrystal silicon intowhich a high concentration of impurities is introduced.

[0205] A source electrode 10 made of a material including, for example,aluminum (Al) is formed on the first main surface so as to beelectrically connected to n⁺ source region 6 and p⁺ contact region 7.

[0206] A drain metal wire 11 is formed on the second main surface so asto contact n⁺ drain region 1.

[0207] Here, in an actual element, a source electrode part iselectrically connected to an n⁺ source region 6 and to a p⁺ contactregion 7 through a contact hole provided in the interlayer insulatingfilm above the first main surface and via a barrier metal. In thepresent invention, however, this part is not important and, therefore,the source electrode part is simplified and is expressed using a solidline throughout the drawings.

[0208] In addition, though in an actual element, n⁺ drain region 1 isseveral times to several tens of times thicker than the thickness of theeffective element portion, n⁺ drain region 1 is expressed as beingthinner than the effective element portion in the drawings for thepurpose of simplification. In addition to the above, scales, ratios ofdimensions, and the like, are deformed in order to simplify theexpression and, therefore, the respective dimensions in the drawings arenot necessarily precise.

[0209] Though in the present embodiment a multiple guard ring structuremade of p-type impurity regions 15 is provided as a terminationstructure of the pn-repeating structure, the structure of this portionis not particularly limited in the present invention and this guard ringstructure may be replaced with another termination structure. Here,termination structures of the other embodiments described below can alsobe replaced in the same manner as in the above.

[0210] The structure of the present embodiment is characterized by thesetting of the impurity concentration in the pn-repeating structure ofn-type drift regions 3 and p-type impurity regions 4.

[0211] A pair made up of n-type impurity region 3 and p-type impurityregion 4 located at the outermost portion, which is the terminationportion of this pn-repeating structure, has the lowest impurityconcentration (or the least general effective charge amount) from amongall of the n-type impurity regions 3 and p-type impurity regions 4forming the pn-repeating structure. That is to say, the closer to thecenter portion are n-type impurity regions 3 and p-type impurity regions4 forming the pn-repeating structure, the higher are the impurityconcentrations (or the greater are the general effective charge amounts)and the closer to the edge portion are n-type impurity regions 3 andp-type impurity regions 4 forming the pn-repeating structure, the lowerare the impurity concentrations (or the smaller are the generaleffective charge amounts).

[0212] Here, though in the present embodiment, a configuration is shownwherein p-type impurity regions 4 are located at the outermost portionson both sides, left and right, of the pn-repeating structure, n-typedrift region 3 may be located at the outermost portions on both sides,left and right, of the pn-repeating structure. In addition, a p-typeimpurity region 4 may be located at one outermost portion of thepn-repeating structure and n-type drift region 3 is located at the otheroutermost portion.

[0213] The pn-repeating structure has a concentration change of threestages (or change in general effective charge amount) in the presentembodiment. n-type drift regions 3 and p-type impurity regions 4 in thecenter portion are a high concentration region, one pair made up ofn-type drift region 3 and p-type impurity region 4 at the outermostportion is a low concentration region and one pair made up of n-typedrift region 3 and p-type impurity region 4 located between the centerportion and the outermost portion is a middle concentration region.

[0214] Here, the difference in these impurity concentrations isdistinguished by the hatching in the drawings of the presentspecification. That is to say, the denser is the hatching, the higher isthe concentration (or the greater is the general effective chargeamount) and the less dense is the hatching, the lower is theconcentration (or the smaller is the general effective charge amount) inthe pn-repeating structure. Here, in some of the below describedembodiments, regions without hatching are also illustrated and indicateregions of the lowest impurity concentration (or the smallest generaleffective charge amount) in the pn-repeating structure.

[0215] Concretely, in the case that the impurity concentration (orgeneral effective charge amount) of high concentration regions 3 and 4is posited as 100%, in general, the impurity concentration (or generaleffective charge amount) of middle concentration regions 3 and 4 is setat 67% and the impurity concentration (or general effective chargeamount) of the low concentration regions 3 and 4 is set at 33% at thetime of division into three. However, it is not always necessary to makea division into three equal parts based on the results of numericalsimulations or experiments. In fact, the respective concentrations (orgeneral effective charge amount) are allowed to have ranges and theimpurity concentration (or general effective charge amount) of themiddle concentration regions 3 and 4 may be approximately 60% to 80%while the impurity concentration (or general effective charge amount) ofthe low concentration regions 3 and 4 may be approximately 20% to 45%.

[0216] In the present embodiment, n-type drift region 3 and p-typeimpurity region 4 at the outermost portion of the pn-repeating structurehave the lowest impurity concentration (or smallest general effectivecharge amount) from among all of the n-type drift regions 3 and p-typeimpurity regions 4 forming the pn-repeating structure. Therefore, abuffer region of middle concentration between the pin diode structure,which is in many cases formed at the outermost portion of thepn-repeating structure, and the repeating cell portion is formed so thatthe difference in the formation of the electrical field distributionoccurring in the respective regions is eased and, therefore, thereduction of the main withstanding voltage in the connection portion canbe restricted to a great extent in comparison with the case wherein therepeating cell portion and the conventional termination structureportion are directly connected.

[0217] Next, the difference between the present invention and the priorart is described.

[0218] As described above, the gist of Prior Art 1 indicates a guidingprinciple of a method for designing the entirety of an element in a formthat includes the termination structure by somehow extending the superjunction structure of the repeating cell portion to the terminationstructure portion. On the other hand, the gist of the present inventionis “a structure, and manufacturing method for the same, wherein a bufferregion of the electrical field between the insides of the cells of ahigh impurity concentration and the termination portion of a lowimpurity concentration at the time when a portion similar to the superjunction effect described in Prior Art 1 wherein a three dimensionalmultiple RESURF effect is used and the termination structure portionhaving an electrical field distribution of a flat trapezoidal form suchas of a pin diode having the conventional structure.” Therefore, thoughPrior Art 1 and the present invention share the same purpose and effectthat a high withstand voltage implemented in the same portion is notlost at the termination portion, they are formed from totally differentpoints of view.

[0219] In addition, the structure of Prior Art 1 is a structure thatincludes a detailed regulation of the structure of the surface portionof a so-called termination structure portion and the presupposedcondition differs from that of the present invention wherein the type ofthe so-called termination structure portion does not matter. On theother hand, according to the present invention, it is possible to adopta combination of a variety of structures such as generally know multipleguard ring structures (FLR, FFR) or a field plate (FP) structure inaddition to the above described “junction termination structure” in thetermination structure so as to have a higher versatility.

[0220] Thus, the present invention presupposes that the concentration ofthe i layer of the pin diode portion including the termination structureformed of a conventional multiple guard ring or of a field plate is setat a low concentration so as to have a higher withstand voltage thanthat obtained in the pn-repeating structure and, therefore, a superjunction structure is not applied in the termination structure portion,unlike the configuration shown in Prior Art 1. In addition, according tothe present invention, a three dimensional multiple RESURF structureportion inside of the cell and a termination structure in a conventionalstructure are not simply combined as in a prior art or in Prior Art 2,shown by FIGS. 148 to 150, and a buffer layer of a middle concentrationis provided so that the change in concentration does not become extreme.

[0221] (Second Embodiment)

[0222] In reference to FIG. 2, the configuration of the presentinvention differs from the configuration shown in FIG. 1 in the pointthat the present embodiment has a configuration wherein theconcentrations of n-type drift regions 3 and p-type impurity regions 4are independently lowered to get lesser in an alternating manner in thedirection toward the edge portion side in four stages without using eachcombination of n-type drift region 3 and p-type impurity region 4(hereinafter referred to as a pn combination) as one unit. That is tosay, p-type impurity region 4 located at the outermost portion of thepn-repeating structure is a region of extremely low concentration havingthe lowest impurity concentration. n-type drift region 3 adjoining thisp-type impurity region 4 at the outermost portion is a low concentrationregion having the next lowest impurity concentration. p-type impurityregion 4 adjoining this n-type drift region 3 on the center portion sideis a middle concentration region having an impurity concentration lowerthan the high concentration region of the center portion and higher thanthe low concentration region.

[0223] Here, the other parts of the configuration are approximately thesame as of the above described configuration of the first embodimentand, therefore, the same symbols are attached to the same members, ofwhich the descriptions are omitted.

[0224] In the present embodiment there is an advantage wherein theconcentration is gradually reduced in multiple stages and, thereby, inpractice, the change can be regarded as being continuous withoutdiscrete stages. There is an advantage wherein the area of a portionhaving a concentration gradient in the termination portion can beeliminated, even though the electrical field distribution form isslightly distorted in comparison with the configuration, wherein theconcentration is reduced in four stages using a unit of a pn combinationin the above described first embodiment.

[0225] Here, in the case that the total area of the element issufficiently large, the area used for the structure of these terminalportions is sufficiently small so that the elimination of the area canbe regarded as having no influence. Accordingly, in such a case, a morestable electrical field distribution form can be obtained by reducingthe concentration using a unit of a pn combination as in the firstembodiment.

[0226] Contrarily, in the case of a comparatively small element area ofapproximately 1 mm by 1 mm, the ratio of the area used for the structureof the termination portion to the entirety of the element becomes highwhen the pn combination is used as a unit and, thereby, there is adisadvantage wherein the on resistance increases (deteriorates).Accordingly, in such a case, the configuration wherein theconcentrations of n-type drift regions 3 and p-type impurity regions 4,without using the pn combination as a unit, are independently lowered iseffective, as in the present embodiment.

[0227] In addition, in the case that the impurity concentration of thehigh concentration regions 3 and 4 is posited as 100%, a concentrationsetting of each region in the case that the concentration gradient hasfour stages, as in the present embodiment, is ideal where the respectiveimpurity concentrations of middle concentration region 4, lowconcentration region 3 and region of extremely low concentration 4 areequally divided so as to be 75%, 50% and 25%. As described in the firstembodiment, however, the impurity concentrations need not be reduced inequal steps so that a certain range is allowed to each of the impurityconcentrations.

[0228] (Third Embodiment)

[0229] In reference to FIG. 3, the configuration of the presentembodiment differs from the configuration of the first embodiment in thepoint wherein the low concentration region at the outermost portion ofthe pn-repeating structure in the configuration of the presentembodiment is formed of only one pair of the pn combination, which isone unit. That is to say, the pair formed of the pn combination 3 and 4located at the outermost portion of the pn-repeating structure has thesame impurity concentration and has an impurity concentration lower thanthat of the high concentration regions 3 and 4 in the center portion.

[0230] In addition, as for the concentration setting of the respectiveregions in the case that the concentration gradient has only one stage,as in the present embodiment, the impurity concentration of each of thelow concentration regions 3 and 4 is preferably no less than 30% and nogreater than 70% in the case that the impurity concentration of the highconcentration regions 3 and 4 is posited as 100%.

[0231] Here, the other parts of the configuration are approximately thesame as in the configuration of the above described first embodimentand, therefore, the same symbols are attached to the same members, ofwhich the descriptions are omitted.

[0232] As described below, there are many cases wherein it is difficultto form low concentration regions because of manufacturing reasons andwherein an increase in the number of steps leads to an extension of themanufacturing period or an increase in costs. It is necessary to reducethe number of low concentration regions in order to avoid such defectsrelated to manufacture.

[0233] (Fourth Embodiment)

[0234] In reference to FIG. 4, the configuration of the presentembodiment differs from the configuration of the first embodiment in thepoint that the low concentration region at the outermost portion in thepn-repeating structure is solely p-type impurity region 4 in the presentembodiment. That is to say, p-type impurity region 4 at the outermostportion of the pn-repeating structure is solely the low concentrationregion while other n-type drift regions 3 and p-type impurity regions 4forming the pn-repeating structure are all high concentration regions.

[0235] Here, the other parts of the configuration are approximately thesame as of the above described configuration of the first embodimentand, therefore, the same symbols are attached to the same members, ofwhich the descriptions are omitted.

[0236] The present embodiment has a structure obtained by furthersimplifying the above described configuration of the third embodimentand, therefore, is effective in, particularly, an element having lowvoltage, low current and small element area and a manufacturing methodfor such an element can also be simplified.

[0237] (Fifth Embodiment)

[0238] In reference to FIG. 5, the configuration of the presentEmbodiment is an example wherein a technique of lowering theconcentration in three stages as shown in FIG. 2 and a technique ofconcentration reduction using the pn combination shown in FIG. 1 as oneunit are combined. That is to say, a pair made up of pn combination 3, 4at the outermost portion in the pn-repeating structure is an extremelylow concentration region having the lowest impurity concentration in thepn-repeating structure. A pair made up of pn combination 3, 4 adjoiningthis extremely low concentration region is a low concentration regionhaving the next lowest impurity concentration. A pair made up of pncombination 3, 4 adjoining this low concentration region is a middleconcentration region having the impurity concentration lower than thatof the pn combination 3, 4 in the center portion and higher than that ofthe low concentration region.

[0239] The configuration of the present embodiment differs from theconfigurations of the first to fourth embodiments in the configurationof the MOS-FET portion. That is to say, though in the configurations ofthe first to fourth embodiments, MOS-FET structures are formed on bothsides of n-type drift layer 3 in a symmetrical manner, a MOS-FETstructure is formed on only one side of n-type drift layer 3 in thepresent embodiment.

[0240] Here, the other parts of the configuration are approximately thesame as of the above described configuration of the first embodimentand, therefore, the same symbols are attached to the same members, ofwhich the descriptions are omitted.

[0241] It is seen that the smaller is the cell repeating period, moreeffectively the three dimensional multiple RESURF effect works due tothe pn-repeating structure. In addition, a small cell pitch is requiredfrom a point of view of making the previous RESURF effect effective.

[0242] In the present embodiment, the MOS-FET structure is formed ononly one side of n-type drift region 3 and, therefore, the cell pitchcan be scaled down. Therefore, though the total channel width (area) ofthe MOS-FET is somewhat sacrificed, the cell pitch can be reduced by upto half without changing the total channel width in comparison with thecase (the first to fourth embodiments) wherein MOS-FETs are formed in asymmetrical manner and, thereby, an increase in the performance of thepn-repeating structure can be achieved.

[0243] (Sixth Embodiment)

[0244] Next, the structure wherein the present invention is applied tothe structure having multiple epitaxial layers is described in the sixthto eighth embodiments.

[0245] In reference to FIG. 6, in the present embodiment, a plurality of(for example, three) p-type impurity regions 4 a forming layers in thedepth direction of the semiconductor substrate is integrated so as toform a p-type impurity region 4 making up the pn-repeating structure.p-type impurity region 4 located at the outermost portion of thepn-repeating structure from among a plurality of p-type impurity regions4 has the lowest impurity concentration forming a low concentrationregion. In addition, each n-type region in an n⁻ epitaxial layer 2placed between each pair of the plurality of p-type impurity regions 4forms an n-type impurity region making up the pn-repeating structure.

[0246] Here, the other parts of the configuration are approximately thesame as of the above described configuration of the first embodimentand, therefore, the same symbols are attached to the same members, ofwhich the descriptions are omitted.

[0247] In the present embodiment, p-type impurity region 4 at theoutermost portion in the pn-repeating structure has the lowest impurityconcentration in the same manner as in the first embodiment and,therefore, the withstand voltage obtained in this outermost portionbecomes high so that an increase in the withstand voltage at the cellportion can be achieved.

[0248] Here, FIG. 6 shows, for the purpose of simplification of thedrawing, a configuration wherein the concentration of only one stagerespectively on both sides of the terminal portions is lowered. As shownin the first to fifth embodiments, however, the concentration gradientlayers of the termination portions may have multiple stages. In the caseof the multiple stages, though a withstand voltage higher than that inthe case of one stage can be obtained, there is a disadvantage that theprocess becomes complex as shown in the description of the process flowin the following.

[0249] In addition, though p-type impurity region 4 has a structureincluding the concentration distribution in the depth direction of thesemiconductor substrate as shown in FIG. 6, a symmetric concentrationrepeated in the lateral direction is discussed in broad perspective inthe present invention and, therefore, a problem caused by such aconcentration distribution in the depth direction can be ignored.

[0250] In addition, though only a two-stage concentration gradient ofp-type impurity region 4 is depicted for the purpose of simplificationin FIG. 6, the concentration of p-type impurity region 4 in actualitychanges without discrete stages and in a continuous manner and changesperiodically in the depth direction of the substrate.

[0251] The configuration (FIG. 6) in the present embodiment differs fromthe configurations of below described Embodiments 7 and 8 in the pointthat an n⁻ epitaxial layer 2 is used as a substrate in this embodiment,wherein the concentration of the layer has been increased to the degreethat the p-type impurity concentration of p-type impurity region 4 isbalanced with that of this layer. As a result, in the presentembodiment, the impurity distribution in a cross section of p-typeimpurity region 4 becomes of a form well-known in Japan as “round sweetballs of confectionary on a skewer.”

[0252] (Seventh and Eighth Embodiments)

[0253] In the pn-repeating structure in the buried multiple epitaxiallayers described so far, a plurality of (for example, three) p-typeimpurity regions 4 a that form layers in the depth direction of thesemiconductor substrate is integrated as shown in FIG. 7 so as to formp-type impurity regions 4 making up the pn-repeating structure. Inaddition, a plurality of (for example, three) n-type impurity regions 3a that form layers in the depth direction of the semiconductor substrateis integrated so as to form n-type drift regions 3 making up thepn-repeating structure. Therefore, each of p-type impurity regions 4 andn-type impurity regions 3 has an impurity concentration distributionthat periodically changes in the depth direction of the substrate.

[0254] An average impurity concentration of each of the plurality ofp-type impurity regions 4 is substantially the same and an averageimpurity concentration of each of the plurality of n-type drift regions3 is also substantially the same.

[0255] This configuration differs from the above described configurationof the sixth embodiment in the point that each of the p-type or n-typeregions forming the pn-repeating structure as described above has aconstant average concentration and that n-type drift regions 3 areformed through a plurality of 4 implantation steps wherein theimplantation energies are changed in the same manner as in p-typeimpurity regions 4 and, therefore, the concentration distribution in thedepth direction of the semiconductor substrate is included in thestructure.

[0256] Though in FIG. 7, the concentration gradients of n-type driftregions 3 and p-type impurity regions 4 in the depth direction of thesemiconductor substrate are depicted as having only two stages for thepurpose of simplification in the same manner as in FIG. 6, in actualitythey change without discrete stages and in a continuous manner. Inaddition, as shown in FIG. 7 the configuration formed according to amethod of diffusing both the p-type impurities and n-type impuritiessimultaneously so as to form the pn-repeating structure does not becomeof a form of “round sweet balls of confectionary on a skewer” as shownin FIG. 6.

[0257] In contrast to this, the configuration of the seventh embodimentshown in FIG. 8 differs from the conventional configuration of FIG. 7 inthe point that the concentration of p-type impurity region 4 at theoutermost portion of the pn-repeating structure in the buried multipleepitaxial layers has been lowered by one stage in the configuration ofthe seventh embodiment.

[0258] In addition, the configuration of the eighth embodiment showingFIG. 9 differs from the conventional configuration of FIG. 7 in thepoint that the concentration of a pair made of the pn combination ofp-type impurity region 4 and n-type drift layer 3 at the outermostportion of the pn-repeating structure in the buried multiple epitaxiallayers is lowered by one stage in the configuration of the eighthembodiment.

[0259] Here, the other parts of the configurations of FIGS. 8 and 9 areapproximately the same as in the configuration shown in FIG. 7 and,therefore, the same symbols are attached to the same members, of whichthe descriptions are omitted.

[0260] In the seventh and eighth embodiments, p-type impurity region 4(and n-type drift layer 3) at the outermost portion in the pn-repeatingstructure has the lowest impurity concentration in the same manner as inthe first embodiment and, therefore, the withstand voltage obtained atthis outermost portion becomes high so that an increase in withstandvoltage in the cell portion can be achieved.

[0261] (Ninth to Twelfth Embodiments)

[0262] Next, the structure wherein the present invention is applied to adiode instead of a MOS-FET is described in the ninth to twelfthembodiments.

[0263] The configurations wherein the MOS-FETs in FIGS. 1, 6 and 9 arereplaced with diodes are shown in FIGS. 10, 11 and 12 as the ninth,tenth and eleventh embodiments, respectively.

[0264] In reference to FIGS. 10 to 12, a p-type impurity region 21 isformed on the first main surface side of the entirety of thepn-repeating structure so as to be electrically connected to an anodeelectrode 22.

[0265] Here, the other parts of the configuration of FIG. 10 areapproximately the same as in the configuration shown in FIG. 1, theother parts of the configuration of FIG. 11 are approximately the sameas in the configuration shown in FIG. 6 and the other parts of theconfiguration of FIG. 12 are approximately the same as in theconfiguration shown in FIG. 9 and, therefore, the same symbols areattached to the same members, of which the descriptions are omitted.

[0266] In addition, the configuration of the twelfth embodiment shown inFIG. 13 differs from the configuration shown in FIG. 5 in the pointsthat a trench 24 is provided in each pn combination in the configurationof the twelfth embodiment and that the MOS-FETs in the configuration ofFIG. 5 are replaced with diodes in the configuration of the twelfthembodiment. Here, in order to replace the MOS-FETs with diodes, a p-typeimpurity region 21 is formed on the first main surface side of theentirety of the pn-repeating structure so as to be electricallyconnected to an anode electrode 22.

[0267] In addition, as for the concentration setting in the pn-repeatingstructure, a technique of lowering the concentration in three stages isused in the terminal portions of the pn-repeating structure in the samemanner as in the structure shown in FIG. 5.

[0268] The other parts of the configuration of FIG. 13 are approximatelythe same as in the configuration shown in FIG. 5 and, therefore, thesame symbols are attached to the same members, of which the descriptionsare omitted.

[0269] In the ninth to twelfth embodiments, p-type impurity region 4(and n-type drift layer 3) at the outermost portion has the lowestimpurity concentration in the pn-repeating structure in the same manneras in the first embodiment and, therefore, the withstand voltageobtained in this outermost portion becomes high and an increase in thewithstand voltage in the cell portion of the diode can be achieved.

[0270] The configurations shown in the ninth to twelfth embodiments areconfigurations wherein, though the upper portion structures are notactive elements, they function as elements that allow high speedswitching at a low ON voltage.

[0271] (Thirteenth to Sixteenth Embodiments)

[0272] Next, the structure that is a diode structure, as the above, andwherein the present invention is applied to a diode of which the upperportion has a Schottky junction is described in the thirteenth tosixteenth embodiments.

[0273] The configurations wherein the diodes in FIGS. 10, 11, 12 and 13are replaced with Schottky diodes are shown in FIGS. 14, 15, 16 and 17as the thirteenth, fourteenth, fifteenth and sixteenth embodiments,respectively.

[0274] In reference to FIGS. 14 to 17, an anode electrode 22 made ofmetal is electrically connected to the first main surface of thesemiconductor substrate and a metal silicide layer 2 la is formed onthis connection portion.

[0275] Here, the other parts of the configuration of FIG. 14 areapproximately the same as in the configuration shown in FIG. 10, theother parts of the configuration of FIG. 15 are approximately the sameas in the configuration shown in FIG. 11, the other parts of theconfiguration of FIG. 16 are approximately the same as in theconfiguration shown in FIG. 12 and the other parts of the configurationof FIG. 17 are approximately the same as in the configuration shown inFIG. 13 and, therefore, the same symbols are attached to the samemembers, of which the descriptions are omitted.

[0276] In the thirteenth to sixteenth embodiments, p-type impurityregion 4 (and n-type drift region 3) at the outermost portion has thelowest impurity concentration in the pn-repeating structure, in the samemanner as in the first embodiment and, therefore, the withstand voltageobtained in this outermost portion becomes high so that an increase inthe withstand voltage in the cell portion of the Schottky diode can beachieved.

[0277] (Seventeenth Embodiment)

[0278] In the present embodiment, an example of a manufacturing methodfor the configuration shown in FIG. 6 is described in reference to FIGS.18 to 25.

[0279] In reference to FIG. 18, an n⁻ epitaxial layer 2 is formed on ann⁺ substrate 1 of a high concentration including arsenic or antimony bymeans of a conventional epitaxial method. This n⁻ epitaxial layer 2 isformed of only one layer having a high and uniform impurityconcentration in comparison with the n-type drift layer concentrationthat is utilized in a MOS-FET of a conventional structure that does notuse a multiple RESURF effect.

[0280] After this, a resist pattern 31 a having a predetermined patternis formed on n⁻ epitaxial layer 2 using photomechanical technology. Ionimplantation of boron ions is carried out at a high energy level byusing this resist pattern 31 a as a mask and, thereby, boron ionimplanted region 4 a is formed at a deep location of the region thatbecomes the center portion of the pn-repeating structure.

[0281] Here, though FIG. 18 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 a, a base silicon oxide film may be provided ifnecessary.

[0282] In reference to FIG. 19, ion implantation of boron ions iscarried out at a middle energy level by using the above described resistpattern 31 a as a mask and, thereby, a boron ion implanted region 4 a isformed at a location at a depth of a middle level that becomes thecenter portion of the pn-repeating structure.

[0283] In reference to FIG. 20, ion implantation of boron ions iscarried out at a low energy level by using the above described resistpattern 31 a as a mask and, thereby, a boron ion implanted region 4 a isformed at a shallow location of a region that becomes the center portionof the pn-repeating structure. After this, resist pattern 31 a isremoved by means of, for example, ashing.

[0284] Here, the order of the respective implantations of the abovedescribed implantation to the deep location (FIG. 18), implantation tothe middle location (FIG. 19) and implantation to the shallow location(FIG. 20) can be switched.

[0285] In reference to FIG. 21, a resist pattern 31 b having apredetermined pattern is formed on n⁻ epitaxial layer 2 usingphotomechanical technology. Ion implantation of boron ions is carriedout at a high energy level by using this resist pattern 31 b as a maskand, thereby, a boron ion implanted region 4 a is formed at a deeplocation of a region that becomes the outermost portion of thepn-repeating structure.

[0286] Here, though FIG. 21 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 a, a base silicon oxide film may be provided ifnecessary.

[0287] In reference to FIG. 22, ion implantation of boron ions iscarried out at a middle energy level by using the above described resistpattern 31 b as a mask and, thereby, a boron ion implanted region 4 a isformed at a location of a middle depth in a region that becomes theoutermost portion of the pn-repeating structure.

[0288] In reference to FIG. 23, ion implantation of boron ions iscarried out at a low energy level by using the above described resistpattern 31 b as a mask and, thereby, a boron ion implanted region 4 a isformed at a shallow location of a region that becomes the outermostportion of the pn-repeating structure. After this, resist pattern 31 bis removed by means of, for example, ashing.

[0289] The implantation concentration of boron ions implanted into theoutermost portion of the pn-repeating structure in the steps of FIGS. 21to 23 is set at approximately half of the implantation concentration ofboron ions implanted into the center portion.

[0290] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 21), implantation to amiddle location (FIG. 22) and implantation to a shallow location (FIG.23) can be switched. Furthermore, the implantation process to give a lowconcentration to these outermost portions can be switched as a wholewith the implantation process to give a high concentration to the abovedescribed center portion.

[0291] In the present embodiment, though a case wherein only column of ap layer of a low concentration is formed at the outermost portion of thepn-repeating structure is cited as an example for simplification, thepresent embodiment is not specifically limited to this case.

[0292] In reference to FIG. 24, a resist pattern 31 c having apredetermined pattern is formed on an n⁻ epitaxial layer 2 usingphotomechanical technology. Ion implantation of boron ions is carriedout at an extremely low energy level by using this resist pattern 31 cas a mask and, thereby, boron ion implanted regions 5 and 15 are formedat very shallow locations of respective regions that become the centerportion, the outermost portion and the guard ring portion, which has thetermination structure, in the pn-repeating structure. After this, resistpattern 31 c is removed by means of, for example, ashing.

[0293] In reference to FIG. 25, heat treatment is carried out at a hightemperature for a long period of time. Thereby, boron ion implantedregions 5 and 15 are diffused to have appropriate sizes so as to form aguard ring portion 15 and a p-type body region 5. At the same time asthis, a plurality of boron ion implanted regions 4 a aligned in thedepth direction of the semiconductor substrate is diffused into thesurroundings so as to be integrated and, thereby, a p-type impurityregion 4 making up the pn-repeating structure is formed. After this,MOS-FET configuration portions, electrodes, or the like, are formed sothat the semiconductor device shown in FIG. 6 is completed.

[0294] The maximum acceleration energy is approximately several Mev,even using current high energy ion implantation technology. Therefore,even boron, which is a light element, has a range in Si of 10 μm, orless, and cannot be implanted into a very deep location. Accordingly,the element structure that can be implemented according to amanufacturing method of the present embodiment is limited to having thecomparatively low withstand voltage of approximately 200 V, or less.

[0295] However, there is an advantage wherein the process is simple incomparison with the below described buried multi-layer epitaxial systemor trench system, even though an expensive manufacturing unit, that isto say a high energy ion implantation unit, and a photoresist for thickfilm and a photomechanical process accompanying this are used.

[0296] (Eighteenth Embodiment)

[0297] An example of a manufacturing method for the configuration shownin FIG. 8 is described in reference to FIGS. 26 to 32 in the presentembodiment.

[0298] The manufacturing method for the present embodiment, at first,includes the same process as the process of the seventeenth embodimentshown in FIGS. 18 to 20. Here, n⁻ epitaxial layer 2 is formed of onlyone layer having a low concentration and a uniform impurityconcentration in comparison with the concentration of n-type driftlayers utilized in a MOS-FET of the conventional structure wherein amultiple RESURF effect is not used.

[0299] After this, in reference to FIG. 26, a resist pattern 31 d havinga predetermined pattern is formed on n⁻ epitaxial layer 2 usingphotomechanical technology. Ion implantation of phosphorus ions iscarried out at a high energy level by using this resist pattern 31 d asa mask and, thereby, an implantation region 3 a of phosphorus ions isformed at a deep location in a region that becomes the center portion ofthe pn-repeating structure.

[0300] Here, though FIG. 26 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 d, a base silicon oxide film may be provided ifnecessary.

[0301] In reference to FIG. 27, ion implantation of phosphorus ions iscarried out at a middle energy level by using the above described resistpattern 31 d as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at location of a middle depth in a region thatbecomes the center portion.

[0302] In reference to FIG. 28, ion implantation of phosphorus ions iscarried out at a low energy level by using the above described resistpattern 31 d as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at a shallow location in a region that becomesthe center portion. After this, resist pattern 31 d is removed by meansof, for example, ashing.

[0303] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 26), implantation to alocation of a middle depth (FIG. 27) and implantation to a shallowlocation (FIG. 28) can be switched. Furthermore, these implantationprocesses of phosphorus ions to the center portion can be switched as awhole with the above described implantation processes of boron ions tothe center portion.

[0304] In reference to FIG. 29, a resist pattern 31 e having apredetermined pattern is formed on n⁻ epitaxial layer 2 usingphotomechanical technology. Ion implantation of boron ions is carriedout at a high energy level by using this resist pattern 31 e as a maskand, thereby, an implantation region 4 a of boron ions is formed at adeep location in a region that becomes the outermost portion of thepn-repeating structure.

[0305] Here, though FIG. 29 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 a, a base silicon oxide film may be provided ifnecessary.

[0306] In reference to FIG. 30, ion implantation of boron ions iscarried out at a middle energy level by using the above described resistpattern 31 e as a mask and, thereby, an implantation region 4 a of boronions is formed at a location of a middle depth in a region that becomesthe outermost portion of the pn-repeating structure.

[0307] In reference to FIG. 31, ion implantation of boron ions iscarried out at a low energy level by using the above described resistpattern 31 e as a mask and, thereby, an implantation region 4 a of boronions is formed at a shallow location in a region that becomes theoutermost portion of the pn-repeating structure. After this, resistpattern 31 e is removed by means of, for example, ashing.

[0308] The implantation concentration of boron ions implanted into theoutermost portion of the pn-repeating structure in the steps of FIGS. 29to 31 is set at approximately half of the implantation concentration ofboron ions implanted into the center portion.

[0309] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 29), implantation to alocation of a middle depth (FIG. 30) and implantation to a shallowlocation (FIG. 31) can be switched. Furthermore, these implantationprocesses of low concentration into the outermost portion of thepn-repeating structure can be switched as a whole with the abovedescribed implantation processes of boron ions or phosphorus ions of ahigh concentration into the center portion.

[0310] Though in the present embodiment a case of the formation only onecolumn of a p layer of a low concentration at the outermost portion ofthe pn-repeating structure is cited as an example for simplification,the present embodiment is not specifically limited to this case.

[0311] In reference to FIG. 32, guard ring portions 15 and p-type bodyregions 5 are formed by carrying out the same process as that of theseventeenth embodiment, shown in FIG. 24. At the same time as this, aplurality of implantation regions 4 a of boron ions and a plurality ofimplantation regions 3 a of phosphorus ions aligned in the depthdirection of the semiconductor substrate are diffused into thesurrounding areas so as to be integrated and p-type impurity regions 4and n-type drift regions 3 making up the pn-repeating structure areformed. After this, MOS-FET configuration portions, electrodes, and thelike, are formed so that the semiconductor device shown in FIG. 8 iscompleted.

[0312] Here, though FIG. 32 represents connected n-type drift regions 3and connected p-type impurity regions 4 in two stages, of lowconcentration and high concentration, for the purpose of simplification,these impurity concentrations in actuality change without discretestages and in a continuous manner and change in an alternating manner inthe depth direction of the substrate. In addition, though p-typeimpurity region 4 of a low concentration at the outermost portion of thepn-repeating structure has a wavy cross sectional form that spreadssomewhat to the outer periphery in a portion having a high impurityconcentration, this detail is omitted for the purpose of simplification.

[0313] In the seventeenth embodiment, p-type impurity regions 4 areformed in n-type epitaxial layer 2 of a comparatively high concentrationthrough boron ion implantation. In contrast to this, in the presentembodiment, n-type epitaxial layer 2 of a low concentration is used sothat respective buried diffusion regions 3 a and 4 a in n-type driftregions 3 and p-type impurity regions 4 are independently formed.Therefore, the concentration of n-type epitaxial layer 2 in the outerperipheral portion of the pn-repeating structure becomes low so as toform a pin diode.

[0314] In addition, since n-type drift regions 3 and p-type impurityregions 4 are formed by means of ion implantations, it is easy tobalance the concentrations of n-type drift regions 3 and p-type impurityregions 4 in comparison with the seventeenth embodiment. Therefore, themanufacturing method according to the present embodiment is a methodsuitable for an element of a comparatively high withstand voltage, evenamong elements having a low withstand voltage.

[0315] However, ion implantation processes for n-type drift regions 3and p-type impurity regions 4 are independently carried out and,therefore, there is a disadvantage wherein the number of steps increasesin comparison with the seventeenth embodiment. Therefore, it ispreferable to choose a method from among these that is appropriate forthe element from the point of view of performance or of cost.

[0316] (Nineteenth Embodiment)

[0317] An example of a manufacturing method for the configuration shownin FIG. 9 is described in reference to FIGS. 33 to 42 in the presentembodiment. Here, according to the following method, it is possible toform the structure shown in FIGS. 1 to 5.

[0318] The manufacturing method of the present embodiment includes, atfirst, the same process as that of the seventeenth embodiment shown inFIGS. 18 to 20. Here, n⁻ epitaxial layer 2 is formed of only one layerhaving a low concentration and a uniform impurity concentration incomparison with the concentration of n-type drift layers utilized in aMOS-FET of the conventional structure wherein a multiple RESURF effectis not used.

[0319] After this, in reference to FIG. 33, a resist pattern 31 f havinga predetermined pattern is formed on n⁻ epitaxial layer 2 according tophotomechanical technology. Ion implantation of phosphorus ions iscarried out at a high energy level by using this resist pattern 31 f asa mask and, thereby, an implantation region 3 a of phosphorus ions isformed at a deep location in a region that becomes the center portion ofthe pn-repeating structure.

[0320] Here, though FIG. 33 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 f, a base silicon oxide film may be provided ifnecessary.

[0321] In reference to FIG. 34, ion implantation of phosphorus ions iscarried out at a middle energy level by using the above described resistpattern 31 f as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at a location of middle depth in a region thatbecomes the center portion.

[0322] In reference to FIG. 35, ion implantation of phosphorus ions iscarried out at a low energy level by using the above described resistpattern 31 f as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at a shallow location in a region that becomesthe center portion. After this, resist pattern 31 f is removed by meansof, for example, ashing.

[0323] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 33), implantation to amiddle location (FIG. 34) and implantation to a shallow location (FIG.35) can be switched. Furthermore, these implantation processes ofphosphorus ions to the center portion can be switched as a whole withthe above described implantation processes of boron ions to the centerportion.

[0324] In reference to FIG. 36, this is the start of a manufacturingprocess of a configuration wherein the concentration is required to belowered. A resist pattern 31 g having a predetermined pattern is formedon n⁻ epitaxial layer 2 according to photomechanical technology. Ionimplantation of phosphorus ions is carried out at a high energy levelusing this resist pattern 31 g as a mask and, thereby, an implantationregion 3 a of phosphorus ions is formed at a deep location in a regionthat is closer to the center portion (front) by one stage from theoutermost portion of the pn-repeating structure.

[0325] Here, though FIG. 36 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 g, a base silicon oxide film may be provided ifnecessary.

[0326] In reference to FIG. 37, ion implantation of phosphorus ions iscarried out at a middle energy level using the above described resistpattern 31 g as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at a location of a middle depth in a regionthat is closer to the center portion by one stage from the outermostportion of the pn-repeating structure.

[0327] In reference to FIG. 38, ion implantation of phosphorus ions iscarried out at a low energy level using the above described resistpattern 31 g as a mask and, thereby, an implantation region 3 a ofphosphorus ions is formed at a shallow location in a region that iscloser to the center portion by one stage from the outermost portion ofthe pn-repeating structure. After this, resist pattern 31 g is removedby means of, for example, ashing.

[0328] The implantation concentration of phosphorus ions implanted tothe outermost portion of the pn-repeating structure in the process ofFIGS. 36 to 38 is set at approximately half of the implantationconcentration of phosphorus ions implanted to the center portion.

[0329] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 36), implantation to amiddle location (FIG. 37) and implantation to a shallow location (FIG.38) can be switched. Furthermore, these implantation processes ofphosphorus ions to a region closer to the center portion by one stagefrom the outermost portion of the pn-repeating structure can be switchedas a whole with the above described implantation processes of boron ionsor phosphorus ions to the center portion.

[0330] In reference to FIG. 39, a resist pattern 31 h having apredetermined pattern is formed on n⁻ epitaxial layer 2 usingphotomechanical technology. Ion implantation of boron ions is carriedout at a high energy level using this resist pattern 31 h as a mask and,thereby, an implantation region 4 a of boron ions is formed at a deeplocation in a region that becomes the outermost portion of thepn-repeating structure.

[0331] Here, though FIG. 39 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 h, a base silicon oxide film may be provided ifnecessary.

[0332] In reference to FIG. 40, ion implantation of boron ions iscarried out at a middle energy level using the above described resistpattern 31 h as a mask and, thereby, an implantation region 4 a of boronions is formed at a location of a middle depth in a region that becomesthe outermost portion of the pn-repeating structure.

[0333] In reference to FIG. 41, ion implantation of boron ions iscarried out at a low energy level using the above described resistpattern 31 h as a mask and, thereby, an implantation region 4 a of boronions is formed at a shallow location in a region that becomes theoutermost portion of the pn-repeating structure. After this, resistpattern 31 h is removed by means of, for example, ashing.

[0334] The implantation concentration of boron ions implanted to theoutermost portion of the pn-repeating structure in the process of FIGS.39 to 41 is set at approximately half of the implantation concentrationof boron ions implanted into the center portion.

[0335] Here, the order of the respective implantations of the abovedescribed implantation to a deep location (FIG. 39), implantation to amiddle location (FIG. 40) and implantation to a shallow location (FIG.41) can be switched. Furthermore, these implantation processes of a lowconcentration of boron ions to the outermost portion can be switched asa whole with the above described implantation processes of a highconcentration of boron ions or phosphorus ions to the center portion orthe implantation process of a low concentration of phosphorus ions to aregion closer to the center portion by one stage from the outermostportion of the pn-repeating structure.

[0336] Though in the present embodiment, a case wherein only one columnof pn combinations made up of p layers and n layers of a lowconcentration is formed at the outermost portion of the pn-repeatingstructure is cited as an example for the purpose of simplification, thepresent invention is not specifically limited to this.

[0337] In reference to FIG. 42, guard ring portions 15 and p-type bodyregions 5 are formed by carrying out the same process as in theseventeenth embodiment, shown in FIG. 24. At the same time as this, aplurality of implantation regions 4 a of boron ions and a plurality ofimplantation regions 3 a of phosphorus ions aligned in the depthdirection of the semiconductor substrate are diffused into thesurrounding areas so as to be integrated and p-type impurity regions 4and n-type drift regions 3 making up the pn-repeating structure areformed. After this, MOS-FET configuration portions, electrodes, and thelike, are formed so that the semiconductor device shown in FIG. 9 iscompleted.

[0338] Here, though FIG. 42 represents connected n-type drift regions 3and connected p-type impurity regions 4 in two stages, of lowconcentration and high concentration, for the purpose of simplification,these impurity concentrations in actuality change without discretestages and in a continuous manner and change in an alternating manner inthe depth direction of the substrate. In addition, though p-typeimpurity region 4 of a low concentration at the outermost portion of thepn-repeating structure has a wavy cross sectional form that spreadssomewhat to the outer periphery in a portion having a high impurityconcentration, this detail is omitted for the purpose of simplification.

[0339] (Twentieth Embodiment)

[0340] A process flow for manufacturing the configuration of FIG. 6 byusing multiple epitaxial layers for the formation of the buried regionsis described in detail in the twentieth embodiment, in reference toFIGS. 43 to 53.

[0341] In reference to FIG. 43, a first stage of n⁻ epitaxial layer 2 ais formed on an n⁺ substrate 1 of high concentration including arsenicor antimony by means of a conventional epitaxial method. This n⁻epitaxial layer 21 is formed of only one layer having a lowconcentration and a uniform impurity concentration in comparison withthe concentration of n-type drift layers utilized in a MOS-FET of theconventional structure wherein a multiple RESURF effect is not used. Aresist pattern 31 i having a predetermined pattern is formed on n⁻epitaxial layer 2 a using photomechanical technology.

[0342] Here, though FIG. 43 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 i, a base silicon oxide film may be provided ifnecessary.

[0343] In reference to FIG. 44, ion implantation of boron ions iscarried out at a conventional energy level by using this resist pattern31 i as a mask and, thereby, an implantation region 4 a of a highconcentration of boron ions is formed at a comparatively shallowlocation (though the location may be deep, in general it is difficult toobtain a high energy level) in a region that becomes the center portion.After this, resist pattern 31 i is removed by means of, for example,ashing.

[0344] In reference to FIG. 45, a resist pattern 31 k having apredetermined pattern is formed on n⁻ epitaxial layer 2 a usingphotomechanical technology. Ion implantation of boron ions is carriedout at a conventional energy level by using this resist pattern 31 k asa mask and, thereby, an implantation region 4 a of a low concentrationof boron ions is formed at a comparatively shallow location in a regionthat becomes the outermost portion of the pn-repeating structure. Afterthis, resist pattern 31 k is removed by means of, for example, ashing.

[0345] Here, though FIG. 45 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 k, a base silicon oxide film may be provided ifnecessary.

[0346] In reference to FIG. 46, an n⁻ epitaxial layer 2 b of a lowconcentration is formed by means of epitaxial growth in the same manneras the process described in FIG. 43 in order to bury implantationregions 4 a of boron ions of both the above described high concentrationand low concentration in the substrate. Strictly speaking, eachimplantation region 4 a slightly diffuses into the surrounding area sothat the cross sectional form thereof becomes circular as a result of aheat treatment in this epitaxial growth process. The diffused state isillustrated in a form of spreading (rising) into the above portion ofthe epitaxial growth interface shown by the dotted line and this rise,itself, is not positively utilized and the rise is not harmful.

[0347] In the following steps, each of the processes, starting from theformation of the above described first stage of n⁻ epitaxial layer 2 a,of the formation of a high concentration boron ion implanted region 4 a,of the formation of a low concentration boron ion implanted region 4 aand of the formation of a second stage of n⁻ epitaxial layer 2 b isessentially repeated a desired number of times.

[0348] In reference to FIG. 47, a resist pattern 31 l having apredetermined pattern is formed on n⁻ epitaxial layer 2 b usingphotomechanical technology. Ion implantation of boron ions is carriedout at a conventional energy level by using this resist pattern 31 l asa mask and, thereby, an implantation region 4 a of a high concentrationof boron ions is formed at a comparatively shallow location of a regionthat becomes the center portion of the pn-repeating structure. Afterthis, resist pattern 31 l is removed by means of, for example, ashing.

[0349] Here, though FIG. 47 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 l, a base silicon oxide film may be provided ifnecessary.

[0350] In reference to FIG. 48, a resist pattern 31 m having apredetermined pattern is formed on n⁻ epitaxial layer 2 b usingphotomechanical technology. Ion implantation of boron ions is carriedout at a conventional energy level by using this resist pattern 31 m asa mask and, thereby, an implantation region 4 a of a low concentrationof boron ions is formed at a comparatively shallow location of a regionthat becomes the outermost portion of the pn-repeating structure. Afterthis, resist pattern 31 m is removed by means of, for example, ashing.

[0351] Here, though FIG. 48 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 m, a base silicon oxide film may be provided ifnecessary.

[0352] After this, a low concentration of n⁻ epitaxial layer 2 c isformed by means of epitaxial growth in the same manner as described inthe process of FIG. 43 in order to bury implantation regions 4 a ofboron ions of both the above described high concentration and lowconcentration in the substrate. Strictly speaking, each implantationregion 4 a slightly diffuses into the surrounding area so that the crosssectional form thereof becomes circular as a result of a heat treatmentin this epitaxial growth process. The diffused state is illustrated in aform of spreading (rising) into the above portion of the epitaxialgrowth interface shown by the dotted line and this rise, itself, is notpositively utilized and the rise is not harmful.

[0353] In reference to FIG. 49, a resist pattern 3 in having apredetermined pattern is formed on n⁻ epitaxial layer 2 c usingphotomechanical technology. Ion implantation of boron ions is carriedout at a conventional energy level by using this resist pattern 31 n asa mask and, thereby, an implantation region 4 a of a high concentrationof boron ions is formed at a comparatively shallow location of a regionthat becomes the center portion of the pn-repeating structure. Afterthis, resist pattern 31 n is removed by means of, for example, ashing.

[0354] Here, though FIG. 49 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 n, a base silicon oxide film may be provided ifnecessary.

[0355] In reference to FIG. 50, a resist pattern 31 o having apredetermined pattern is formed on n⁻ epitaxial layer 2 c usingphotomechanical technology. Ion implantation of boron ions is carriedout at a conventional energy level by using this resist pattern 31 o asa mask and, thereby, an implantation region 4 a of a low concentrationof boron ions is formed at a comparatively shallow location of a regionthat becomes the outermost portion of the pn-repeating structure. Afterthis, resist pattern 31 o is removed by means of, for example, ashing.

[0356] Here, though FIG. 50 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 o, a base silicon oxide film may be provided ifnecessary.

[0357] In reference to FIG. 51, the final stage of n⁻ epitaxial layer 2d of a low concentration is formed by means of epitaxial growth in thesame manner as described in the process of FIG. 43 in order to buryimplantation regions 4 a of boron ions of both the above described highconcentration and low concentration in the substrate. Thereby, amulti-layer epitaxial layer 2 is formed of n⁻ epitaxial layers 2 a to 2d.

[0358] Strictly speaking, each implantation region 4 a slightly diffusesinto the surrounding area so that the cross sectional form thereofbecomes circular as a result of a heat treatment in this epitaxialgrowth process. The diffused state is illustrated in a form of spreading(rising) into the above portion of the epitaxial growth interface shownby the dotted line and this rise, itself, is not positively utilized andthe rise is not harmful.

[0359] In reference to FIG. 52, a resist pattern 31 p having apredetermined pattern is formed on an n⁻ epitaxial layer 2 d usingphotomechanical technology. Ion implantation of boron ions is carriedout at an extremely low energy level by using this resist pattern 31 pas a mask and, thereby, implantation regions 5 and 15 of boron ions areformed at very shallow locations of the respective regions that becomethe center portion and the outermost portion of the pn-repeatingstructure as well as the guard ring portion that has the terminationstructure. After this, resist pattern 31 p is removed by means of, forexample, ashing.

[0360] In reference to FIG. 53, a heat treatment at a high temperatureis carried out for a long period of time. Thereby, the implantationregions 5 and 15 of boron ions are diffused so as to have appropriatesizes so that guard ring portions 15 and p-type body regions 5 areformed. At the same time as this, a plurality of boron ion implantedregions 4 a aligned in the depth direction of the semiconductorsubstrate is diffused into the surroundings so as to be integrated and,thereby, a p-type impurity region 4 making up the pn-repeating structureis formed. After this, MOS-FET configuration portions, electrodes, orthe like, are formed so that the semiconductor device shown in FIG. 6 iscompleted.

[0361] Here, the implantation concentration of boron ions implanted intothe outermost portion of the pn-repeating structure in the steps of FIG.45, FIG. 48 and FIG. 50 is set at approximately half of the implantationconcentration of boron ions implanted into the center portion.

[0362] In addition, though in the present embodiment a case wherein theconcentration of the outermost portion of the pn-repeating structure islowered by only one stage is cited as an example and described, it ispossible to lower the concentration in a plurality of stages as in theother above described examples. Thereby, even though there is a drawbackwherein the process becomes more complex and the manufacturing costincreases, there is a great advantage that the withstand voltageperformance of an element is improved. Accordingly, the concentrationmay be lowered in multiple stages in accordance with the relationshipbetween the price and performance of the required products and thepresent embodiment is definitely not limited to the structure whereinthe concentration is lowered in one stage or to the manufacturing methodfor such a structure.

[0363] According to a manufacturing method of the present embodiment,epitaxial layers can, in principle, be infinitely stacked by increasingthe number of layers. Therefore, a semiconductor device obtainedaccording to this manufacturing method can deal with withstand voltagesin a range of from a middle withstand voltage of several hundreds V to ahigh withstand voltage of several thousands V. Contrarily, as describedbelow, a heat treatment process at a relatively high temperature isalways required in order to connect buried diffusion regions 4 a in thedepth direction. Not only diffusion in the depth direction (upward anddownward direction), but also diffusion in the lateral direction, occursimultaneously as a result of this high temperature heat treatment and,therefore, the length of the repeating pn unit cannot be shortened sothat there is a drawback wherein it is difficult to obtain fullperformance in the low withstand voltage region beneath approximately300 V.

[0364] (Twenty-First Embodiment)

[0365] A process flow for manufacturing the configuration of FIG. 6 byusing multi-layered epitaxial layer for the formation of a buried regionand by using a strip pattern for diffusion at the outermost portion ofthe pn-repeating structure is described in detail as the twenty-firstembodiment in reference to FIGS. 54 to 63.

[0366] In reference to FIG. 54, a first stage of n⁻ epitaxial layer 2 ais formed on an n⁺ substrate 1 of a high concentration including arsenicor antimony by means of a conventional epitaxial method. This n⁻epitaxial layer 2 a is formed of only one layer having a lowconcentration and a uniform impurity concentration in comparison withthe concentration of the n-type drift layer utilized in a MOS-FET of theconventional structure wherein a multiple RESURF effect is not used. Aresist pattern 31 q having a predetermined pattern is formed on n⁻epitaxial layer 2 a by means of photomechanical technology.

[0367] A first opening pattern including a single hole is formed in aregion that becomes the center portion of the pn-repeating structure ofthis resist pattern 31 q while a second opening pattern including aplurality of microscopic holes is formed in a region that becomes theoutermost portion of the pn-repeating structure. The sum of the areas ofthe openings of all of the microscopic holes in the second openingpattern is set to be smaller than the area of the opening of the firstopening pattern.

[0368] Here, though FIG. 54 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 q, a base silicon oxide film may be provided ifnecessary.

[0369] In reference to FIG. 55, ion implantation of boron ions iscarried out at a conventional energy level by using this resist pattern31 q as a mask. Thereby, an implantation region 4 a of a highconcentration of boron ions is formed at a comparatively shallowlocation in a region that becomes the center portion of the pn-repeatingstructure and an implantation region 4 a of a low concentration of boronions is formed at a comparatively shallow location in a region thatbecomes the outermost portion of the pn-repeating structure,respectively.

[0370]FIG. 63 shows the state of impurity implantation at the outermostportion of the pn-repeating structure immediately after the abovedescribed ion implantation. In reference to FIG. 63, the second openingpattern above the outermost portion of the pn-repeating structure isformed of a plurality of microscopic holes and, therefore, implantationregions 4 a ₁ of boron ions are formed directly beneath the respectivemicroscopic holes. A heat treatment for impurity diffusion is carriedout on the substrate in this condition.

[0371] In the case that the plurality of microscopic holes created arevery fine, a slight heat treatment makes the plurality of implantationregions 4 a _(i) of boron ions spread and diffuse into the surroundingareas, as shown in FIG. 64, so as to overlap each other and so as tobecome integrated to form an implantation region 4 a of a lowconcentration. In addition, a slight heat treatment enables therespective implantation regions 4 a _(i) to easily overlap throughlateral diffusion so that the concentration becomes uniform as a whole.Though this implantation region 4 a of a low concentration hasunevenness in form and concentration, it can macroscopically be regardedas a uniform diffusion region 4 a of a comparatively low concentration.In addition, the above described heat treatment itself can be carriedout as a part of an epitaxial growth process in the following steps orcan be independently carried out before the epitaxial growth.

[0372] Here, the sum of the areas of the openings of all of themicroscopic holes in the second opening pattern is set to become smallerthan the area of the opening of the first opening pattern. Therefore,even though ion implantation to both of these opening patterns iscarried out at the same time, implantation region 4 a of a highconcentration can be formed in a region that becomes the center portionand implantation region 4 a of a low concentration can be formed in aregion that becomes the outermost portion of the pn-repeating structure,respectively.

[0373] After this, resist pattern 31 q is removed by means of, forexample, ashing.

[0374] In reference to FIG. 56, an n⁻ epitaxial layer 2 b of a lowconcentration is formed through epitaxial growth in the same manner asdescribed in the process of FIG. 54 in order to bury both of the abovedescribed implantation regions 4 a of boron ions of a high concentrationand of a low concentration in the substrate. Strictly speaking, eachimplantation region 4 a slightly diffuses into the surrounding area sothat the cross sectional form thereof becomes circular as a result of aheat treatment in this epitaxial growth process. The diffused state isillustrated in a form of spreading (rising) into the above portion ofthe epitaxial growth interface shown by the dotted line and this rise,itself, is not positively utilized and the rise is not harmful.

[0375] In the following process, the respective steps, starting from theformation of the above described first stage n⁻ epitaxial layer 2 a, ofthe formation of implantation region 4 a of a high concentration ofboron ions, of the formation of implantation region 4 a of a lowconcentration of boron ions and of the formation of a second stage n⁻epitaxial layer 2 b are essentially repeated a desired number of times.

[0376] In reference to FIG. 57, a resist pattern 31 r having apredetermined pattern is formed on n⁻ epitaxial layer 2 a by means ofphotomechanical technology in the same manner as in FIG. 54. A firstopening pattern made of a single hole in this resist pattern 31 r isformed above a region that becomes the center portion of thepn-repeating structure and a second opening pattern made of a pluralityof microscopic holes is formed above a region that becomes the outermostportion of the pn-repeating structure. The sum of the areas of theopenings of all of the microscopic holes in the second opening patternis set to be smaller than the area of the opening of the first openingpattern.

[0377] Here, though FIG. 57 shows a case of direct photoresistapplication wherein a base silicon oxide film is not provided beneathresist pattern 31 r, a base silicon oxide film may be provided ifnecessary.

[0378] After this, ion implantation of boron ions is carried out at aconventional energy level by using this resist pattern 31 r as a mask.Thereby, an implantation region 4 a of a high concentration of boronions is formed at a comparatively shallow location in a region thatbecomes the center portion of the pn-repeating structure and animplantation region 4 a of a low concentration of boron ions is formedat a comparatively shallow location in a region that becomes theoutermost portion of the pn-repeating structure, respectively. Afterthis, resist pattern 31 r is removed by means of, for example, ashing.

[0379] In reference to FIG. 58, epitaxial growth is carried out in thesame manner as in the above and, thereby, an n⁻ epitaxial layer 2 c of alow concentration is formed. Strictly speaking, each implantation region4 a slightly diffuses into the surrounding area so that the crosssectional form thereof becomes circular as a result of a heat treatmentin this epitaxial growth process.

[0380] After this, additionally, an implantation region 4 a of a highconcentration of boron ions is formed at a comparatively shallowlocation in a region that becomes the center portion of the pn-repeatingstructure and an implantation region 4 a of a low concentration of boronions is formed at a comparatively shallow location in a region thatbecomes the outermost portion of the pn-repeating structure,respectively, by means of a single photomechanical process and a singleion implantation in the same manner as described above. After this,resist pattern 31 s is removed by means of, for example, ashing.

[0381] In reference to FIG. 59, epitaxial growth is carried out in thesame manner as above and, thereby, an n⁻ epitaxial layer 2 d of a lowconcentration is formed. Strictly speaking, each implantation region 4 aslightly diffuses into the surrounding area so that the cross sectionalform thereof becomes circular as a result of a heat treatment in thisepitaxial growth process.

[0382] In reference to FIG. 60, a resist pattern 31 t having apredetermined pattern is formed on n⁻ epitaxial layer 2 d by means ofphotomechanical technology. Ion implantation of boron ions is carriedout at an extremely low energy level by using this resist pattern 31 tas a mask and, thereby, implantation regions 5 and 15 of boron ions areformed at very shallow locations in the respective regions that becomethe center portion and the outermost portion of the pn-repeatingstructure as well as a guard ring portion that is the terminationstructure. After this, resist pattern 31 t is removed by means of, forexample, ashing.

[0383] Here, though it is desirable from a practical point of view toprovide a base silicon oxide film at the time of the photomechanicalprocess, the embodiment is not specifically limited to this and,therefore, the base silicon oxide film is omitted in the drawings forthe purpose of simplification.

[0384] In reference to FIG. 61, a heat treatment at high temperature fora long period of time is carried out. Thereby, implantation regions 5and 15 of boron ions are diffused to appropriate sizes so that guardring portion 15 and p-type body region 5 are formed. At the same time asthis, a plurality of implantation regions 4 a of boron ions aligned inthe depth direction of the semiconductor substrate is diffused to thesurrounding areas so as to be integrated and, thereby, a p-type impurityregion 4, forming the pn-repeating structure, is formed.

[0385] In reference to FIG. 62, an n⁺ source region 6 and a p⁺ contactregion 7 for making a low resistance contact with a p-type body region 5are formed within the p-type body region 5 by means of conventionalphotomechanical technology and by means of ion implantation technology.

[0386] Here, n⁺ source region 6 is formed of arsenic or phosphorus andp⁺ contact region 7 is formed of boron, respectively, and, therefore, itis necessary to independently carry out a photomechanical process and anion implantation process for forming n⁺ source region 6 and p⁺ contactregion 7. In addition, the order of these processes relative to thebelow described formation of a gate region is not specifically definedand the order can be switched according to the performance orapplication.

[0387] Finally, the semiconductor device shown in FIG. 6 is completed bycompleting the MOS-FET structures. Here in FIG. 6, contact holes via theinterlayer insulating film are omitted and Al wires, and the like, aresimplified so as to be shown as simple straight line wires.

[0388] In addition, though in the present embodiment a case wherein theconcentration of the outermost portion of the pn-repeating structure islowered in only one stage is cited as an example and is described, it ispossible to lower the concentration in a plurality of stages as in theother above described examples. Thereby, though there is a drawback thatthe process becomes more complicated and the manufacturing cost rises,there is a great advantage wherein the withstand voltage performance ofan element is improved. Therefore, the concentration may be lowered inmultiple stages according to the relationship between the price andperformance of the required products and the present embodiment isdefinitely not limited to the structure having one stage or to amanufacturing method for such a structure.

[0389] According to a manufacturing method for a device of amulti-layered system used in the present embodiment, the manufactureddevice can cope with a high withstand voltage in a range from a middlewithstand voltage of approximately several hundreds V to a highwithstand voltage of several thousands V while having the drawback ofpoor performance in the low withstand voltage region beneathapproximately 300 V. On the other hand, the outermost portion of thepn-repeating structure can be formed at the same time as the centerportion through modification of the manufacturing method of the presentembodiment, in contrast to the twentieth embodiment, and, therefore,there is an advantage wherein the manufacturing steps can be halved.

[0390] (Description of the Case of Embodiment Having Trenches)

[0391] A process flow for manufacturing a pn-repeating structure in thecenter portion in the case that there are trenches in the structure isbriefly described in the following, though this is not a directembodiment, and, after that, an embodiment of the present inventionwherein the structure having these trenches and a manufacturing methodfor such a structure are applied is described.

[0392] In addition, there is an advantage to this structure STM (SuperTrench power MOS-FET) having trenches wherein not only the number ofsteps is fewer but, also, wherein the tradeoff relationship between themain withstanding voltage and the ON resistance of an element is verygood since the length of repetition can easily be shortened to the limitin comparison with the above described buried multi-layer epitaxialstructure and manufacturing method for the same and, therefore, there isalso an advantage wherein the element is, in principle, effective in abroad range from a low withstand voltage to a high withstand voltage,from the point of view of manufacturing technology.

[0393] A process flow for creating diffusion layers in the trenchsidewalls through diagonal ion implantation is described sequentially inreference to FIGS. 65 to 69.

[0394] In reference to FIG. 65, first, anisotropic etching is carriedout by using a silicon oxide film, or the like, formed by means of a CVDmethod as a mask material 41 according to a conventional method and,thereby, a plurality of trenches 23 are created in the first mainsurface of the semiconductor substrate.

[0395] In reference to FIG. 66, boron ions are implanted into thesidewalls on only one side of trenches 23 created in a stripe form and,thereby, boron ion implantation regions 4 are formed.

[0396] In reference to FIG. 67, phosphorus ions are implanted into thesidewalls only on the opposite side of trenches 23 created in a stripeform and, thereby, phosphorus ion implantation regions 3 are formed.Here, the steps of these FIGS. 66 and 67 may be switched.

[0397] In reference to FIG. 68, p-type impurity regions 4 and n-typedrift regions 3 having desired impurity concentration profiled areformed by carrying out simultaneous diffusion of boron ion implantedregions 4 and phosphorus ion implantation regions 3 by means of a heattreatment.

[0398] In reference to FIG. 69, trenches 23 are filled in with aninsulator 24, such as a silicon oxide film, formed by means of a CVDmethod.

[0399] As described above, the STM structure is excellent in performanceand from the point of view of manufacturing cost in comparison with theburied multi-layer epitaxial structure. However, the technique ofdiagonal ion implantation into the sidewalls on only one side oftrenches 23, which is seldom used for manufacturing LSIs (Large ScaleIntegrated circuits), is used. Therefore, there is a drawback whereinthe process becomes complicated and the difficulty in setting theconditions of manufacture increases at the time when the concentrationof the outermost portion in the pn-repeating structure is lowered, incomparison with the case of the above described buried multi-layerepitaxial process. Accordingly, it is preferable to manufacture asemiconductor device of the present invention by selecting a suitablemanufacturing method from among several types, including of thisembodiment, according to the index listing cost and performance requiredfor the product.

[0400] (Twenty-Second Embodiment)

[0401] A manufacturing method for an STM structure in the case whereinthe trenches in the outermost portion where the concentration of thediffusion layers is lowered are again excavated, separately from thetrenches in the center portion, is described in detail in reference toFIGS. 70 to 78.

[0402] The following steps shown in FIGS. 70 to 72 are extremely thesame as those of the above described process flow of FIGS. 65 to 67.

[0403] In reference to FIG. 70, first, anisotropic etching is carriedout by using a silicon oxide film, or the like, formed by means of a CVDmethod as a mask material 41 a according to a conventional method and,thereby, a plurality of trenches 23 is created in the first main surfaceof a semiconductor substrate. A trench located at the outermost portionin the finished condition is not included in these trenches 23.

[0404] In reference to FIG. 71, boron ions are implanted into all of thesidewalls on one side of the plurality of trenches 23 created in astriped form and, thereby, boron ion implanted regions 4 are formed.

[0405] In reference to FIG. 72, phosphorus ions are implanted into allof the sidewalls on only the opposite side of the plurality of trenches23 formed in a striped form and, thereby, phosphorus ion implantedregions 3 are formed. Here, these processes of FIGS. 71 and 72 may beswitched and, essentially, the order is not important.

[0406] In reference to FIG. 73, all trenches 23 are once filled in witha film 41 b, such as a silicon oxide film, formed by means of a CVDmethod and the surface is flattened. The process up to this point is thepart of the process corresponding to a manufacturing method for aconventional STM structure and the following is the process with respectto the present embodiment.

[0407] A window is opened at a desired location of film 41 b that isutilized for filling in trenches 23 by means of a conventionalphotomechanical process and by means of anisotropic etching in order tocreate a trench at the outermost portion.

[0408] In reference to FIG. 74, trench 23 at the outermost portion iscreated by carrying out anisotropic etching on the semiconductorsubstrate through the window opened in film 41 b.

[0409] In reference to FIG. 75, boron ions are implanted into thesidewall on only one side of trench 23 at the outermost portion so thata boron ion implanted region 4 is formed. At this time, boron ions areimplanted having a concentration of approximately half that of theimplantation concentration of boron ions that have been implanted in thecenter portion.

[0410] In reference to FIG. 76, phosphorus ions are implanted to thesidewall on the opposite side of trench 23 at the outermost portion sothat a phosphorus ion implanted region 3 is formed. At this time,phosphorus ions are implanted having a concentration of approximatelyhalf that of the implantation concentration of phosphorus ions that havebeen implanted in the center portion. Here, the step of phosphorusimplantation may be switched with the above step of boron implantationand the order thereof is not important.

[0411] In reference to FIG. 77, a heat treatment is carried out on theentirety of the element so that mesa regions located between trenches 23have desired concentration distributions. Thereby, boron ion implantedregions 4 and phosphorus ion implanted regions 3 diffuse into thesurrounding areas so that p-type impurity regions 4 and n-type driftregions 3 are formed. p-type impurity region 4 and n-type drift region 3diffused from the sidewalls of trench 23 at the outermost portion areset to have lower impurity concentrations than those in the centerportion, as described above, and, therefore, the concentrations thereofbecome lower than the impurity concentrations in the center portion inthe finished condition. The part of the process up to this pointconcerns the present embodiment.

[0412] As for the back-end process, as shown in FIG. 78, an insulatingfilm 24 is filled in within trenches 23. Here, this step of the fillingin of the insulating film and the previous heat treatment process may beswitched. In addition, though the step of forming comparatively deepdiffusion regions, such as a guard ring portion that is the terminationstructure and p-type body regions of the MOS-FETs, is not illustrated,they can be appropriately inserted somewhere in the above describedprocess or somewhere in the back-end process.

[0413] Here, though in the present embodiment, a case wherein theconcentration of only one trench 23 at the outermost portion is loweredis cited as an example and is described, it is possible to lower theconcentration in a plurality of stages, as shown in the other abovedescribed examples or in the below described example of an STM structurein FIG. 88. Thereby, there is a great advantage wherein the withstandvoltage performance of an element is improved even though there is thedrawback wherein the process becomes more complicated and themanufacturing cost increases. Therefore, the concentration may belowered in multiple stages according to the relationship between priceand performance of the required products and the present embodiment isdefinitely not limited to the structure having one stage or to amanufacturing method for such a structure.

[0414] (Twenty-Third Embodiment)

[0415] A manufacturing method in the case that ion implantation of theopposite conductive type, that is to say counter ion implantation, iscarried out to the sidewalls of the trench at the outermost portionwherein the concentrations of the diffusion layers are lowered in an STMstructure is described in detail as the twenty-third embodiment inreference to FIGS. 79 to 86.

[0416] In reference to FIG. 79, anisotropic etching is carried out byusing a silicon oxide film that is formed by means of a CVD method, orthe like, as a mask material 41 c according to a conventional methodand, thereby, a plurality of trenches 23 is simultaneously created inthe first main surface of a semiconductor substrate. The trench locatedat the outermost portion in the repeating structure in the finishedcondition is included in these trenches 23.

[0417] In reference to FIG. 80, boron ions of the same implantationconcentration are implanted into all of the sidewalls on one side of theplurality of trenches 23 created in a striped form and, thereby, boronion implanted regions 4 are formed.

[0418] In reference to FIG. 81, phosphorus ions of the same implantationconcentration are implanted into all of the sidewalls only on theopposite side of the plurality of trenches 23 created in a striped formand, thereby, phosphorus ion implanted regions 3 are formed. Here, thesteps of these FIGS. 80 and 81 may be switched and the order is notessentially important.

[0419] In reference to FIG. 82, all trenches 23 are once filled in witha film 41 d, such as a silicon oxide film, formed by means of a CVDmethod. The part of the process up to this point corresponds to amanufacturing method for the conventional STM structure and thefollowing is a process concerning the present embodiment.

[0420] After this, a photoresist pattern 31 u having a window abovetrench 23 located at the outermost portion is formed by means ofphotomechanical technology. Etching is carried out by using this resistpattern 31 u as a mask. In this etching process, wet-type, dry-typeetching or a combination of both is appropriately selected according tothe absolute depth, the aspect ratio, and the like, of trenches 23 thatare to be formed.

[0421] After this, resist pattern 31 u is removed by means of, forexample, ashing.

[0422] In reference to FIG. 83, the filling within trench 23 located atthe outermost portion is removed through the above described etching.

[0423] In reference to FIG. 84, phosphorus ions (n-type) of a conductivetype opposite to that of boron (p-type) that was implanted in theprevious step is implanted into the sidewall on only one side of trench23 at the outermost portion and, thereby, a phosphorus ion implantedregion 3 b is formed. This implantation of phosphorus ions controls thefinished condition of p-type impurity region 4 formed on the sidewall oftrench 23 at the outermost portion to have an impurity concentration ofapproximately half of the concentration of the impurities that have beenimplanted in the center portion.

[0424] In reference to FIG. 85, boron (p-type) of a conductive typeopposite to that of phosphorus ions (n-type) that was implanted in theprevious step is implanted into the sidewall on only the opposite sideof trench 23 at the outermost portion and, thereby, a boron ionimplanted region 4 b is formed. This implantation of boron ions controlsthe finished condition of n-type impurity region 3 formed on thesidewall of trench 23 at the outermost portion to have an impurityconcentration of approximately half of the concentration of theimpurities that have been implanted in the center portion.

[0425] Here, the step of boron implantation may be switched with theprevious step of phosphorous implantation and the order thereof is notimportant. The part of the process up to this point is characteristic ofthe present embodiment. The same flow of a process of another embodimentis briefly described in the following.

[0426] In reference to FIG. 86, a heat treatment is carried out on theentirety of the element so that mesa regions placed between trenches 23have desired concentration distributions. Thereby, boron ion implantedregions 4 and phosphorous ion implanted regions 3 diffuse to thesurrounding areas so as to form p-type impurity regions 4 and n-typedrift regions 3. The impurity concentrations of p-type impurity region 4and n-type drift region 3 diffused from the sidewalls of trench 23 atthe outermost portion are set lower than those of the center portion asdescribed above and, therefore, become lower than those of the centerportion in the finished condition.

[0427] As for the back-end process, as shown in FIG. 78, an insulatingfilm 24 is filled into trenches 23. Here, this process of the filling inof insulating film 24 and the previous heat treatment process may beswitched. In addition, though the process of forming comparatively deepdiffusion regions such as a guard ring portion that is the terminationstructure and p-type body regions of MOS-FETs are not illustrated, theycan be appropriately inserted somewhere in the above described processor somewhere in the back-end process.

[0428] Here, though in the present embodiment a case wherein theconcentration of one trench 23 at the outermost portion is lowered issited as an example and is described, it is possible to lower theconcentration in a plurality of stages as shown in the above describedother examples or in the below described example of an STM structure inFIG. 88. Thereby, there is a great advantage that the withstand voltageperformance of an element is improved though there is the drawbackwherein the process becomes more complicated and the manufacturing costincreases. Accordingly, the concentration may be lowered in multiplestages in accordance with the relationship between price and performanceof the required products and the present embodiment is definitely notlimited to the structure having one stage or to a manufacturing methodfor such a structure.

[0429] An advantage of the method of the present embodiment is that theprocess becomes simple in comparison with the case of the twenty-secondembodiment wherein trenches 23 are excavated twice. Though trenchetching is an established technology, the depth required for thiselement is in many cases much deeper than that of the trenches utilizedin the isolation process of a conventional LSI so that a problem arisesthat the processing period of time becomes long. With respect to thispoint, an advantage is obtained wherein only the buried oxide film isremoved in the portion where the counter doping is carried out so thatthe processing period of time becomes short and the process becomessimple in the case that the process shown in the present embodiment isused. On the other hand, there is a drawback that the setting of theconditions for either wet-type or dry-type etching is difficult in orderto remove the silicon oxide film filled in within a trench of a highaspect ratio.

[0430] (Twenty-Fourth Embodiment)

[0431] A configuration and a manufacturing method are described indetail as the twenty-fourth embodiment in reference to FIGS. 87 to 91 inthe case that the dotted line trench (hereinafter referred to as DLT)structure of the trench at the outermost portion in the repeatingstructure is applied in an STM having a structure wherein the gates areparallel to the trenches and in the case that the concentration of onlyone of the p layer or the n layer of the outermost portion in thepn-repeating structure is lowered. Here, FIG. 88 is a three-dimensionalbird's-eye view showing a configuration wherein a DLT structure isapplied in the trench at the outermost portion in an STM having thestructure where the gates are parallel to the trenches shown in FIG. 87.

[0432] In reference to FIGS. 87 and 88, the configuration of the presentembodiment differs from the configuration shown in FIG. 5 in the pointthat a trench 23 is provided between a pair made of a p-type impurityregion 4 and an n-type drift region 3 in a pn combination in the presentembodiment, in the point that the concentration of the pn combination islowered only in one stage at the outermost portion of the pn-repeatingstructure of the present embodiment and in the point that trench 23located at the outermost portion of the plurality of trenches 23 has aDLT structure in the present embodiment.

[0433] In reference to primarily FIG. 88, here the trenches of the DLTstructure are trenches wherein a plurality of holes 23 a are arranged atintervals in a predetermined direction and, thereby, the trenches have asurface pattern of a dotted line form in the first main surface. Here,each trench 23 is filled in with an insulating film 24 made of, forexample, a silicon oxide film.

[0434] The other parts of the configuration are approximately the sameas the configuration shown in FIG. 5 and, therefore, the same symbolsare attached to the same members, of which the descriptions are omitted.

[0435] The present embodiment is characterized by a structure closelyrelated to its manufacturing method wherein the number of the steps isnot increased and wherein an element having a high main withstandvoltage can be implemented according to the same manufacturing processfor an STM having the conventional structure. In addition, though thereis a drawback that the manufacturing steps increase and becomecomplicated in the case that the concentration gradient in multiplestages is formed in the outermost portion of the pn-repeating structureaccording to the above described other embodiments, there is a greatadvantage wherein the DLT structures shown in the present embodiment andin the following embodiments can be implemented very easily and whereinits manufacturing steps do not generally increase, though the patterndimensions are restricted, even in the case the concentration is loweredin multiple stages.

[0436] At the time when the configuration of FIGS. 87 and 88 ismanufactured, the finished concentration of the low concentration regionat the outermost portion of the pn-repeating structure is determined bythe relationship (effective sidewall area) between length LA, of thesidewalls of each hole 23 a, and length LB, of the intervals betweenholes 23 a. Concretely, concentration lowering ratio Rlc can beapproximately defined by the following equation using the ratio oflength LA to length LB shown in the figure.

Rlc=LA/(LA+LB)

[0437] When LA=2 μm and LB=2 μm, for example, Rlc=50% whereinapproximately the same effect as that of lowering the impurityconcentration of the low concentration region at the outermost portionin the pn-repeating structure by 50% is obtained. Strictly speaking,this impurity concentration changes due to the total amount, temperatureand period of time of the heat treatment after the ion implantation.However, in the case that the conditions are adjusted so that theimpurities diffuse by roughly the same distance as the width LB=2 μm ofthe regions into which impurities are not implanted, impurity atomslocated at the center of a straight line portion (region wherein hole 23a is created) into which impurities are implanted reach to the centerportion of a region into which impurities are not implemented. Theimpurity atoms located at an edge (edge of hole 23 a) of a straight lineportion reach to the edge of the adjoining straight line portion intowhich impurities are simultaneously implanted. Therefore, theconcentration of the straight line portions LA into which impurities arenot implanted and the concentration of the regions LB into whichimpurities are implanted are averaged so as to be lowered toapproximately 50% of the concentration immediately after theimplantation. In the case that the concentration is lowered in one stageas shown in FIGS. 87 and 88, it is preferable for this Rlc to be no lessthan 30% and no greater than 70%.

[0438] In general, the impurity concentration profile in silicon has aform defined by Gaussian distribution or by error function and canalmost be regarded as a primary function, that is to say a triangulardistribution, in the case that these distributions are seen on a linearscale. Accordingly, a large gap does not, in fact, occur in the abovedescribed approximation and, therefore, the concentration can be verysimply adjusted according to the ratio of length LA of the dotted lineto interval LB.

[0439] Here, the dimensions in the direction perpendicular to length LAand LB, that is to say the width of trenches 23, does not related tothis calculation of ratio.

[0440] The contents of the above description are represented so thatthey can be intuitively understood in the following FIGS. 89 to 91. FIG.89 shows the condition immediately after implantation or of insufficientheat treatment wherein high concentration regions 3 and 4 still remainin the sidewalls of trenches 23 in the DLT structure and shows thecondition wherein diffusion regions 3 and 4 of the dotted line form arenot connected.

[0441] Next, FIG. 90 shows the condition wherein impurity regions 3 and4 have diffused through diffusion in the lateral direction by carryingout a slight heat treatment after implantation. High concentrationregions diffuse from the sidewalls of trenches 23 in the DLT structureso as to be connected to other high concentration regions 3 and 4 as aresult of this heat processing. However, high concentration regionsstill remain in portions close to the sidewalls of trenches 23 in theDLT structure. Though there is no major problem in such a state,diffusion by means of a heat treatment is desirable until the entiretyhas been made uniform, as shown in the below described FIG. 91.

[0442] Then, FIG. 91 shows the state wherein high concentration regions3 and 4 are sufficiently diffused from the sidewalls of trenches 23 inthe DLT structure through lateral direction diffusion by applying asufficient heat treatment after implantation so as to be connected toother high concentration regions and so that the concentration of thesidewalls of trenches 23 in the DLT structure becomes approximatelyuniform.

[0443] In addition, Table 1 shows an improved effect in the case thatthe DLT structure is applied to an STM of the 300 V class.

[0444] Comparison of embodiments and prior art regarding withstandvoltage in the dotted line trench structure TABLE 1 structure mainwithstanding voltage (V) ratio (%) simulation in center cell 325 100portion only measurement of the 301 92.6 embodiment wherein 60% isconverted to dotted line measurement of uniform 275 84.6 concentrationin a prior art

[0445] Since an infinitely repeating structure without a terminationportion cannot be manufactured in an actual element, “simulation in thecenter cell portion only” in Table 1 shows, as the ideal case, values inthe case that the main withstanding voltage of the cell portion iscalculated using a numerical value simulation. In this case, the mainwithstanding voltage of 325 V is obtained and this withstand voltagevalue is assumed to be 100% so as to be compared with other measuredvalues.

[0446] On the other hand, “measurement of uniform concentration in priorart” is the case wherein a DLT structure, shown in the presentembodiment, is not used and the obtained withstand voltage is 275 V,which is low, so that it is seen that only 84.6% of the withstandvoltage value is obtained in comparison with the case of ideal cellsonly as described above. Then, a DLT structure, shown in the presentembodiment, is used so as to obtain a prototype of the structure whereinthe ratio of the dotted line portion is 60%, which is approximatelyhalf, and then 301 V is obtained. This is 92.6% of the main withstandingvoltage in the case of the ideal cell portion only and, therefore, it isseen that the main withstanding voltage is increased to a great extent.

[0447] In addition, though the details are omitted, it is seen fromexperiment that a value closer to an ideal value can be obtained byincreasing the number of dotted lines, that is to say, by increasing thenumber of stages in the concentration gradient.

[0448] (Twenty-Fifth Embodiment)

[0449] A case wherein trenches having a DLT structure are used in an STMhaving a structure where gates are parallel to trenches in the samemanner as in the twenty-fourth embodiment and wherein the concentrationof the pn combinations at the outermost portions on both the left andright sides in the pn-repeating structure is lowered in three stages isdescribed in detail as the twenty-fifth embodiment in reference to FIGS.92 and 93. Here, FIG. 93 is a three-dimensional bird's-eye view showinga configuration wherein a DLT structure is used for three trenches at anoutermost portion of the repeating structure in FIG. 92.

[0450] In reference to FIGS. 92 and 93, the configuration of the presentembodiment differs from the configuration shown in FIGS. 87 and 88 inthe point that the pn combination of an outermost portion of thepn-repeating structure is lowered in three stages in the presentembodiment and in the point the DLT structure is used for three trenchesat the outermost portion of the repeating structure in the presentembodiment.

[0451] In the present embodiment, the length and intervals of the dottedlines three trenches 23 at the outermost portion having the DLTstructure are adjusted in order to lower the concentration of the pncombination at the outermost portion of the pn-repeating structure inthree stages based on the concentration lowering ratio described in thetwenty-fourth embodiment. That is to say, the concentration loweringratio Rlc of trenches 23 of a DLT structure made of a plurality of holes23 a ₃ is smaller than the concentration lowering ratio Rlc of trenches23 of a DLT structure made of a plurality of holes 23 a ₂ and theconcentration lowering ratio Rlc of trenches 23 of a DLT structure madeof a plurality of holes 23 a ₂ is smaller than the concentrationlowering ratio Rlc of trenches 23 of a DLT structure made of a pluralityof holes 23 a ₁.

[0452] Here, the other parts of the configuration are approximately thesame as in the configuration shown in FIG. 5 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0453] In the present embodiment, the length and intervals of the dottedlines of trenches 23 are adjusted and, thereby, the concentrationgradient in multiple stages can easily be formed.

[0454] (Twenty-Sixth Embodiment)

[0455] A process flow in the case that trenches of a DLT structure areused for an STM of a structure where gates are parallel to trenches isdescribed in detail as the twenty-sixth embodiment in reference to FIGS.94 and 95.

[0456] A manufacturing method of the present embodiment follows the samesteps as the steps shown in FIGS. 79 to 81. Thereby, a plurality oftrenches 23 is created in the first main surface and a boron ionimplanted region 4 is formed in the sidewall on one side of each trench23 while a phosphorus ion implanted region 3 is formed in the sidewallon the other side, respectively. Here, in the step of FIG. 79, trenches23 at the outermost portions on both the left and right sides of therepeating structure are created so as to have a DLT structure.

[0457] After this, in reference to FIG. 94, a heat treatment is carriedout on the entirety of the device so that mesa regions located betweentrenches 23 have desired concentration distributions. As a result ofthis heat treatment, boron ion implanted region 4 and phosphorus ionimplanted region 3 in the sidewalls of the trench of the DLT structureat an outermost portion of the repeating structure are diffused so thatthe concentrations thereof are lowered and made uniform and, then,become lower than the impurity concentration of the mesa regions in thecenter portion.

[0458] In reference to FIG. 95, an insulator 24 is filled in within eachtrench 23. Here, the step of filling in an insulator and the previousheat treatment step may be switched.

[0459] In addition, though the step of forming comparatively deepdiffusion regions, such as a guard ring or p-type body regions of theMOS-FETs, is not illustrated, it can be appropriately inserted somewherein the above described steps or somewhere after these steps.

[0460] In addition, though in the present embodiment a case wherein theconcentration of only one pair made of a pn combination is lowered ineach of the outermost portions on both the left and right sides of thepn-repeating structure is cited as an example, the process flow may beexactly the same as the above description in the case that theconcentration gradient is formed in multiple stages by using thismanufacturing process. Thereby, an element of a high withstand voltagehaving a concentration gradient of multiple stages can be manufacturedwithout increasing the number of manufacturing steps.

[0461] (Twenty-Seventh Embodiment)

[0462] A configuration having a twin trench structure in the centerportion and having a MOS-FET structure in the active element portion isdescribed in detail in reference to FIG. 9 and, in addition, amanufacturing method for creating a trench at the outermost portion of arepeating structure through excavation carried out two times isdescribed in detail in reference to FIGS. 97 to 105 as thetwenty-seventh embodiment.

[0463] In reference to FIG. 96, the structure of the present embodimentdiffers from the configuration of FIG. 87 in the point that a mesaportion has a twin trench structure and in the point that the outermostportions of both the left and right sides of the pn-repeating structureare formed of one pair of p-type impurity regions 4 and one pair ofn-type impurity regions 3 in order to lower the concentrations.

[0464] Here, the twin trench structure is a configuration whereinimpurity regions of the same conductive type, respectively, exist ineach of the two sidewalls of a trench 23.

[0465] In addition, a pair of p-type impurity regions 4 and one pair ofn-type impurity regions 3 having impurity concentrations lower thanthose in the center portion (impurity concentrations of approximatelyhalf of those in the center portion) are formed at the outermostportions on both the left and right sides in the pn-repeating structure.

[0466] Here, the other parts of the configuration are approximately thesame as in the configuration shown in FIG. 87 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0467] Next, a manufacturing method of the present embodiment isdescribed.

[0468] In reference to FIG. 97, first, anisotropic etching is carriedout by using a silicon oxide film, or the like, formed by means of a CVDmethod as a mask material 41 e according to a conventional method and,thereby, a first group of trenches made up of a plurality of trenches 23is created in the first main surface of a semiconductor substrate. Thisfirst group of trenches does not include trenches located at theoutermost portions of the repeating structure in the finished condition.

[0469] In reference to FIG. 98, phosphorus ions are implanted in thesidewalls on both sides of the entirety of a plurality of trenches 23forming the first group of trenches so as to have a comparatively highconcentration and, then, phosphorous ion implanted regions 3 are formed.After this, film 41 e is removed through etching, or the like.

[0470] In reference to FIG. 99, a film 41 f, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in the entiretyof the plurality of trenches 23 of the first group of trenches accordingto a conventional method. This film 41 f is patterned by means ofphotomechanical technology and etching technology. Anisotropic etchingis carried out by using the patterned film 41 f as a mask material.Thereby, a plurality of trenches 23 forming a second group of trenchesis created so that the respective trenches thereof are located inalternation with the respective trenches 23 of the first group oftrenches. This second group of trenches does not include trencheslocated at the outermost portions of the repeating structure in thefinished condition.

[0471] In reference to FIG. 100, boron ions are implanted in thesidewalls on both sides of the entirety of a plurality of trenches 23forming the second group of trenches so as to have a comparatively highconcentration and, then, boron ion implanted regions 4 are formed. Afterthis, film 41 f is removed through etching, or the like. Here, thesesteps in FIGS. 98 and 100 may be switched and the order thereof is notessentially important. The process up to this point is a manufacturingmethod for a conventional type twin trench structure. The followingprocess is a process by which the present embodiment is characterized.

[0472] In reference to FIG. 101, a film 41 g, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in the entiretyof the plurality of trenches 23 of the first and second groups oftrenches according to a conventional method. This film 41 g is patternedby means of photomechanical technology and etching technology so that aportion above an area that is located one stage before the outermostportion in the pn-repeating structure is opened. Anisotropic etching iscarried out by using the patterned film 41 g as a mask material.Thereby, a first outermost trench 23 is created in a region one stagebefore the outermost portion of the repeating structure.

[0473] In reference to FIG. 102, phosphorus ions are implanted into thesidewalls on both sides of the first outermost trench 23 so as to have acomparatively low concentration and, then, phosphorous ion implantedregions 3 are formed. After this, film 41 g is removed by means ofetching, or the like.

[0474] In reference to FIG. 103, a film 41 h, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in the entiretyof the plurality of trenches 23 of the first and second groups oftrenches and the first outermost trench 23 according to a conventionalmethod. This film 41 h is patterned by means of photomechanicaltechnology and etching technology so that a portion above an area thatbecomes the outermost portion in the pn-repeating structure is opened.Anisotropic etching is carried out by using the patterned film 41 h as amask material. Thereby, a second outermost trench 23 is created in aregion that becomes the outermost portion of the repeating structure.

[0475] In reference to FIG. 104, boron ions are implanted into thesidewalls on both sides of the second outermost trench 23 so as to havea comparatively low concentration and, then, boron ion implanted regions4 are formed. After this, film 41 h is removed by means of etching, orthe like. Here, these steps in FIGS. 102 and 104 may be switched and theorder thereof is not essentially important.

[0476] In reference to FIG. 105, a film 24, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in all oftrenches 23 according to a conventional method. After this, a heattreatment is carried out on the entirety of the element so that mesaregions placed between trenches 23 have desired concentrationdistributions. Thereby, boron ion implanted regions 4 and phosphorousion implanted regions 3 are diffused into the surrounding areas so thatp-type impurity regions 4 and n-type drift regions 3 are formed. Theconcentrations of p-type impurity regions 4 and n-type drift regions 3that have been diffused from the sidewalls of the first and secondoutermost trenches 23 are set to be lower than the impurityconcentrations in the center portion, as described above, and,therefore, they become lower than the impurity concentrations in thecenter portion in the finished condition. Here, this heat treatmentprocess and the previous step of the filling in of insulating film 24may be switched.

[0477] After this, a guard ring portion, which is the terminationstructure, and a MOS-FET portion are formed so that the semiconductordevice shown in FIG. 96 is completed.

[0478] In the twin trench structure according to the present embodiment,the length of the repeating pn unit in the pn-repeating structurebecomes twice as long as that of the STM structure making it difficultfor a three-dimensional multiple RESURF effect to be implemented and,therefore, the main withstanding voltage tends to become lower in thehigh concentration region even in the ideal case. In addition,manufacture includes a complex process such that deep trenches arecreated twice.

[0479] On the other hand, in the twin trench structure, it is notnecessary to take into consideration the complex physically phenomenonwherein the effective concentration is lowered due to the diffusion ofrecoil ions to the opposite side because the same ion species areimplanted into both sidewalls of a trench. Therefore, there is anadvantage such that the manufacturing margin (process window) is greatwith respect to the trench form wherein, even in the case of theoccurrence of a slight bend or slope, there is no major influencetherefrom.

[0480] (Twenty-Eighth Embodiment)

[0481] A manufacturing method for creating a trench at an outermostportion of the repeating structure in the configuration (FIG. 96) havinga twin trench structure in the center portion and having a MOS-FETstructure in the active element portion by lowering the concentrationthrough a counter doping method, that is to say, a method wherein twoimplantations of ion species of opposite conductive types are carriedout, is described in detail as the twenty-eighth embodiment, inreference to FIGS. 106 to 115.

[0482] In reference to FIG. 106, first, anisotropic etching is carriedout by using a silicon oxide film, or the like, formed by means of a CVDmethod as a mask material 41 i according to a conventional method and,thereby, a first group of trenches made of a plurality of trenches 23 iscreated in the main surface of a semiconductor substrate. This firstgroup of trenches includes a trench located at an outermost portion ofthe repeating structure in the finished condition.

[0483] In reference to FIG. 107, phosphorus ions are implanted in thesidewalls on both sides of the entirety of the plurality of trenches 23forming the first group of trenches so as to have a comparatively highconcentration and, then, phosphorous ion implanted regions 3 are formed.After this, film 41 i is removed through etching, or the like.

[0484] In reference to FIG. 108, a film 41 j, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in the entiretyof the plurality of trenches 23 of the first group of trenches accordingto a conventional method. This film 41 j is patterned by means ofphotomechanical technology and etching technology. Anisotropic etchingis carried out by using the patterned film 41 j as a mask material.Thereby, a plurality of trenches 23 forming a second group of trenchesis created so that the respective trenches thereof are located inalternation with the respective trenches 23 of the first group oftrenches. This second group of trenches includes a trench located at anoutermost portion of the repeating structure in the finished condition.

[0485] In reference to FIG. 109, boron ions are implanted into thesidewalls on both sides of the entirety of the plurality of trenches 23forming the second group of trenches so as to have a comparatively highconcentration and, then, boron ion implanted regions 4 are formed. Afterthis, film 41 j is removed through etching, or the like. Here, thesesteps in FIGS. 107 and 109 may be switched and the order thereof is notessentially important. The process up to this point is a manufacturingmethod for a conventional type twin trench structure. The followingprocess is a process by which the present embodiment is characterized.

[0486] In reference to FIG. 110, film 41 k, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in the entiretyof the plurality of trenches 23 according to a conventional method.

[0487] In reference to FIG. 111, this film 41 k is patterned by means ofphotomechanical technology and etching technology and, thereby, aportion above a first outermost trench located one stage before theoutermost portion of the repeating structure is opened. Anisotropicetching is carried out by using the patterned film 41 k as a maskmaterial. Thereby, the filling within first outermost trench 23 isremoved.

[0488] In reference to FIG. 112, boron ions are implanted into thesidewalls on both sides of first outermost trench 23 so as to have acomparatively low concentration and, then, boron ion implanted regions 4b are formed. After this, film 41 k is removed by means of etching, orthe like.

[0489] In reference to FIG. 113, a film 41 l, such as a silicon oxidefilm, is formed by means of a CVD method so as to fill in all trenches23 according to a conventional method. This film 41 l is patterned bymeans of photomechanical technology and etching technology so that aportion above a second outermost trench 23 located at the outermostportion of the repeating structure is opened. Anisotropic etching iscarried out by using the patterned film 41 l as a mask material.Thereby, the filling within second outermost trench 23 is removed.

[0490] In reference to FIG. 114, phosphorus ions are implanted into thesidewalls on both sides of second outermost trench 23 so as to have acomparatively low concentration and, then, phosphorous ion implantedregions 3 b are formed. After this, film 41 l is removed by means ofetching, or the like. Here, these steps in FIGS. 112 and 114 may beswitched and the order thereof is not essentially important.

[0491] In reference to FIG. 115, a film 24, such as a silicon oxidefilm, is formed according to a CVD method so as to fill in all trenches23 according to a conventional method. After this, a heat treatment iscarried out on the entirety of the element so that mesa regions placedbetween trenches 23 have desired concentration distributions. Thereby,boron ion implanted regions 4 and phosphorous ion implanted regions 3are diffused into the surrounding areas so that p-type impurity regions4 and n-type drift regions 3 are formed. In the sidewalls of first andsecond outermost trenches 23, impurities of opposite conductive typescancel each other through counter doping. Therefore, the impurityconcentrations of impurity regions 3 and 4 located in the sidewalls offirst and second outermost trenches 23 becomes lower than the impurityconcentrations in the center portion. Here, this heat processing stepand the previous step of filling in of insulating film 24 may beswitched.

[0492] After this, a guard ring portion, which is the terminationstructure, and the MOS-FET portions are formed so that the semiconductordevice shown in FIG. 96 is completed.

[0493] In the twin trench structure according to the present embodiment,the length of the repeating pn unit in the pn-repeating structurebecomes twice as long as that of the STM structure making it difficultfor a three-dimensional multiple RESURF effect to be implemented and,therefore, the main withstanding voltage tends to become lower in thehigh concentration region even in the ideal case. In addition,manufacture includes a complex process such that deep trenches arecreated twice.

[0494] On the other hand, in the twin trench structure, it is notnecessary to take into consideration the complex physically phenomenonwherein the effective concentration is lowered due to the diffusion ofrecoil ions to the opposite side and a uniform concentration profilefrom the top to the bottom of the trenches can be obtained because thesame ion species are implanted into both sidewalls of a trench.Therefore, there is an advantage such that the manufacturing margin(process window) is great with respect to the trench form wherein, evenin the case of the occurrence of a slight bend or slope, there is nomajor influence therefrom.

[0495] (Twenty-Ninth Embodiment)

[0496] In reference to FIG. 116, the configuration of the presentembodiment shares with the configuration shown in FIG. 96 the point thatthe center portion has a twin trench structure and the active elementportion has a MOS-FET structure and differs from the configuration shownin FIG. 96 in the point that the concentration of only a pair of p-typeimpurity regions 4 at the outermost portion in the pn-repeatingstructure is lowered in the present embodiment.

[0497] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 96 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0498] The configuration of the present embodiment is a configurationwherein the concentration of only the p-type impurity regions at theoutermost portion of the pn-repeating structure is lowered in only onestage and, therefore, has an advantage that the manufacture thereof iseasy. The configuration of the present embodiment can be implementedaccording to the above described twenty-seventh embodiment or thetwenty-eighth embodiment and can also be implemented according to thebelow described thirty-third embodiment.

[0499] (Thirtieth Embodiment)

[0500] In reference to FIG. 117, the configuration of the presentembodiment shares the point that the center portion has a twin trenchstructure with the configuration shown in FIG. 96 and differs from theconfiguration shown in FIG. 96 in the point that the active elementportion has a pin diode structure in stead of a MOS-FET structure and inthe point that the concentration of only a pair of p-type impurityregions 4 at the outermost portion of the repeating structure islowered.

[0501] The pin diode is formed of a p-type impurity region 21 that isformed on the first main surface side of the entirety of thepn-repeating structure and that is electrically connected to an anodeelectrode 22.

[0502] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 96 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0503] The configuration of the present embodiment can be implementedaccording to the above described twenty-seventh embodiment or thetwenty-eighth embodiment and can also be implemented according to thebelow described thirty-third embodiment.

[0504] (Thirty-First Embodiment)

[0505] In reference to FIG. 118, the configuration of the presentembodiment shares the point that the center portion has a twin trenchstructure with the configuration shown in FIG. 96 and differs from theconfiguration shown in FIG. 96 in the point that the active elementportion has a Schottky barrier diode structure instead of a MOS-FETstructure and in the point that the concentration of only a pair ofp-type impurity regions 4 at the outermost portion of the pn-repeatingstructure in the present embodiment.

[0506] The Schottky barrier diode is formed of the entirety of thepn-repeating structure on the first main surface side that iselectrically connected to an anode electrode 22 via a metal silicidelayer 21 a.

[0507] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 96 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0508] The configuration of the present embodiment can be implementedaccording to the above described twenty-seventh embodiment or thetwenty-eighth embodiment and can also be implemented according to thebelow described thirty-third embodiment.

[0509] (Thirty-Second Embodiment)

[0510] In reference to FIG. 119, the configuration of the presentembodiment shares with the configuration shown in FIG. 96 the point thatthe center portion has a twin trench structure and the active elementportion has a MOS-FET structure and differs from the configuration shownin FIG. 96 in the point that an active element is not provided above apair of p-type impurity regions 4 at the outermost portion in thepn-repeating structure in the present embodiment.

[0511] p-type impurity regions 21 are formed above the pair of p-typeimpurity regions 4 at the outermost portion of the pn-repeatingstructure and are electrically connected to a source electrode 10.

[0512] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 96 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0513] (Thirty-Third Embodiment)

[0514] A manufacturing method of simultaneously forming highconcentration regions in the center portion and low concentrationregions at the outermost portion of the pn-repeating structure throughone ion implantation by using a DLT structure for the twin trenchstructure is described in detail as the thirty-third embodiment inreference to FIGS. 106 to 110.

[0515] In reference to FIG. 106, first, anisotropic etching is carriedout by using a silicon oxide film, or the like, formed by means of a CVDmethod as a mask material 41 i according to a conventional method and,thereby, a first group of trenches including a plurality of trenches 23in the center portion and trenches 23 of a DLT structure placed outsidethereof is simultaneously created in the first main surface of asemiconductor substrate. Here, the number of trenches 23 of a DLTstructure may be any number that is no less than one.

[0516] In reference to FIG. 107, phosphorous ions are implanted into thesidewalls on both sides of the entirety of the plurality of trenches 23forming the first group of trenches so that phosphorous ion implantedregions 3 are formed. After this, film 41 i is removed by means ofetching, or the like.

[0517] In reference to FIG. 108, a film 41 j such as a silicon oxidefilm is formed by means of a CVD method so as to fill in the entirety ofthe plurality of trenches 23 of the first group of trenches. This film41 j is patterned by means of photomechanical technology and etchingtechnology. Anisotropic etching is carried out by using the patternedfilm 41 j as a mask material. Thereby, a plural number of trenches 23 inthe center portion and trenches 23 of a DLT structure placed outsidethereof are created forming a second group of trenches so as to locatedin alternation with the respective trenches 23 of the first group oftrenches. Here, the number of trenches 23 of a DLT structure may be anynumber that is no less than one.

[0518] In reference to FIG. 109, boron ions are implanted into thesidewalls on both sides of the entirety of the plurality of trenches 23forming the second group of trenches so that boron ion implanted regions4 are formed. After this, film 41 j is removed by means of etching, orthe like. Here, these steps in FIGS. 107 and 109 may be switched and theorder thereof is not essentially important.

[0519] In reference to FIG. 110, a film 41 k such as a silicon oxidefilm is formed by means of a CVD method so as to fill in the entirety ofthe plurality of trenches 23 according to a conventional method.

[0520] After this, a heat treatment is carried out on the entirety ofthe element so that mesa regions placed between trenches 23 have desiredconcentration distributions. As a result of this heat treatment, theconcentrations of boron ion implanted regions 4 and phosphorous ionimplanted regions 3 in the sidewalls of trenches 23 of a DLT structureat the outermost portion of the repeating structure are diffused so asto be lowered and uniformed and so as to be lower than the impurityconcentration of the mesa regions in the center portion.

[0521] Here, the step of the filling in of an insulator and the previousheat treatment step may be switched.

[0522] In addition, though the process of forming comparatively deepdiffusion regions such as a guard ring and p-type body regions of theMOS-FETs is not illustrated, it can properly be inserted somewhere inthe above described steps or somewhere after these steps.

[0523] (Thirty-Fourth Embodiment)

[0524] A manufacturing method for a pn-repeating structure havingbi-pitch units wherein p-type impurity regions and n-type drift regionsare formed through separate ion implantations is described in detail inreference to FIGS. 120 to 128.

[0525] First, a manufacturing method of the present embodiment followsthe step shown in FIG. 79. Thereby, a plurality of trenches 23 iscreated in the main surface of a semiconductor substrate.

[0526] After this, in reference to FIG. 120, a film 41 m such as asilicon oxide film is formed by means of a CVD method so as to fill inall trenches 23 according to a conventional method.

[0527] In reference to FIG. 121, this film 41 m is patterned by means ofphotomechanical technology and etching technology so that a portionabove every other trench 23 from among the plurality of trenches 23 isopened. Anisotropic etching is carried out by using the patterned film41 m as a mask material. Thereby, the filling within every other trench23 is removed. Phosphorous ions are implanted into the sidewalls on bothsides of every other trench 23 from which the filling has been removedso as to have a comparatively high concentration and, then, phosphorousion implanted regions 3 are formed. After this, film 41 m is removed bymeans of etching, or the like.

[0528] In reference to FIG. 122, a film 41 n such as a silicon oxidefilm is formed by means of a CVD method so as to fill in all trenches 23according to a conventional method. This film 41 n is patterned by meansof photomechanical technology and etching technology so that respectiveportions above the other set of every other trench 23 are opened.Anisotropic etching is carried out by using the patterned film 41 n as amask material. Thereby, the filling within the other set of every othertrench 23 is removed.

[0529] Boron ions are implanted into the sidewalls on both sides of theother set of every other trench 23 from which the filling has beenremoved so as to have a comparatively high concentration and, then,boron ion implanted regions 4 are formed. After this, film 41 n isremoved by means of etching, or the like. Here, these steps in FIGS. 121and 122 may be switched and the order thereof is not essentiallyimportant.

[0530] In reference to FIG. 123, a film 41 o such as a silicon oxidefilm is formed by means of a CVD method so as to fill in all trenches 23according to a conventional method. The process up to this point is aprocess for forming a structure having the repetition of the samebi-pitch units as in a twin trench structure of a conventional structureand the following process is a process for forming a concentrationlowering structure at the outermost portion of the pn-repeatingstructure according to the present embodiment.

[0531] In reference to FIG. 124, this film 41 o is patterned by means ofphotomechanical technology and etching technology so that a portionabove a first outermost trench 23 located one stage before the outermostportion of the repeating structure is opened. Anisotropic etching iscarried out by using the patterned film 41 o as a mask material.Thereby, the filling within first outermost trench 23 is removed.

[0532] In reference to FIG. 125, boron ions are implanted into thesidewalls on both side of first outermost trench 23 so as to have acomparatively low concentration (concentration of approximately half ofthe impurity concentration of phosphorous ion implanted regions 3) sothat boron ion implanted regions 4 b are formed. After this, film 41 ois removed by means of etching, or the like.

[0533] In reference to FIG. 126, a film 41 p such as a silicon oxidefilm is formed by means of a CVD method so as to fill in all trenches 23according to a conventional method. This film 41 p is patterned by meansof photomechanical technology and etching technology so that a portionabove a second outermost trench 23 located at the outermost portion ofthe repeating structure is opened. Anisotropic etching is carried out byusing the patterned film 41 p as a mask material. Thereby, the fillingwithin second outermost trench 23 is removed.

[0534] In reference to FIG. 127, phosphorous ions are implanted into thesidewalls on both side of second outermost trench 23 so as to have acomparatively low concentration (concentration of approximately half ofthe impurity concentration of boron ion implanted regions 4) so thatphosphorous ion implanted regions 3 b are formed. After this, film 41 pis removed by means of etching, or the like. Here, these steps in FIGS.125 and 127 may be switched and the order thereof is not essentiallyimportant.

[0535] In reference to FIG. 128, a film 24 such as a silicon oxide filmis formed by means of a CVD method so as to fill in all trenches 23according to a conventional method. After this, a heat treatment iscarried out on the entirety of the element so that mesa regions placedbetween trenches 23 have desired concentration distributions. Thereby,the impurities of boron ion implanted regions 4 and phosphorous ionimplanted regions 3 are diffused into the surrounding areas so thatp-type impurity regions 4 and n-type drift regions 3 are formed. Theimpurities of opposite conductive types cancel each other because ofcounter doping in the sidewalls of first and second outermost trenches23. Therefore, the impurity concentrations of impurity regions 3 and 4located in the sidewalls of first and second outermost trenches 23become lower than the impurity concentration in the center portion.Here, this heat treatment process and the previous process of thefilling in of insulating film 24 may be switched.

[0536] After this, a guard ring portion that is the terminationstructure and MOS-FET portions are formed so that the semiconductordevice shown in FIG. 96 is completed.

[0537] Here, in the case that the region wherein the concentration islowered is set in multiple stages, the above described step of counterdoping may be repeated a plurality of times.

[0538] (Thirty-Fifth Embodiment)

[0539] A manufacturing method, wherein a method of one-time excavationfor the creation of a trench and of separately implanting ions forp-type impurity regions and n-type drain regions only through bi-pitchimplantations is used for a trench of a DLT structure at the outermostportion of the repeating structure, is described in detail in referenceto FIGS. 120 to 123.

[0540] In reference to FIG. 120, first, a first group of trenches madeof a plurality of trenches 23 in the center portion and trenches 23 of aDLT structure placed outside thereof and a second group of trenches madeof a plurality of trenches 23 in the center portion and trenches 23 of aDLT structure placed outside thereof are created in the first mainsurface of a semiconductor substrate. The respective trenches 23 of thefirst group of trenches and the respective trenches 23 of the secondgroup of trenches are created so as to be positioned in alternation.Here, the respective numbers of trenches 23 of a DLT structure of thefirst and second groups of trenches may be any number that is no lessthan one

[0541] After this, a film 41 m such as a silicon oxide film is formed bymeans of a CVD method so as to fill in all trenches 23 according to aconventional method.

[0542] In reference to FIG. 121, this film 41 m is patterned by means ofphotomechanical technology and etching technology so that a portionabove every other trench 23 from among the plurality of trenches 23 isopened. Anisotropic etching is carried out by using the patterned film41 m as a mask material. Thereby, the filling within every other trench23 is removed. Phosphorous ions are implanted into the sidewalls on bothsides of every other trench 23 from which the filling has been removedso that phosphorous ion implanted regions 3 are formed. After this, film41 m is removed by means of etching, or the like.

[0543] In reference to FIG. 122, a film 41 n such as a silicon oxidefilm is formed by means of a CVD method so as to fill in all trenches 23according to a conventional method. This film 41 n is patterned by meansof photomechanical technology and etching technology so that respectiveportions above the other set of every other trench 23 from among theplurality of trenches 23 are opened. Anisotropic etching is carried outby using the patterned film 41 n as a mask material. Thereby, thefilling within the other set of every other trench 23 is removed.

[0544] Boron ions are implanted into the sidewalls on both sides of theother set of every other trench 23 from which the filling has beenremoved so that boron ion implanted regions 4 are formed. After this,film 41 n is removed by means of etching, or the like. Here, these stepsin FIGS. 121 and 122 may be switched and the order thereof is notessentially important.

[0545] In reference to FIG. 123, a film 41 o such as a silicon oxidefilm is formed by means of a CVD method so as to fill in all trenches 23according to a conventional method.

[0546] After this, a heat treatment is carried out on the entirety ofthe element so that mesa regions placed between trenches 23 have desiredconcentration distributions. As a result of this heat treatment, theconcentrations of boron ion implanted regions 4 and phosphorous ionimplanted regions 3 in the sidewalls of trenches 23 of a DLT structureat the outermost portion of the repeating structure are diffused so asto be lowered and uniformed and so as to be lower than the impurityconcentration of the mesa regions in the center portion.

[0547] Here, the step of the filling in of an insulator and the previousheat treatment step may be switched.

[0548] In addition, though the process of forming comparatively deepdiffusion regions such as a guard ring and p-type body regions of theMOS-FETs is not illustrated, it can properly be inserted somewhere inthe above described steps or somewhere after these steps.

[0549] (Thirty-Sixth Embodiment)

[0550] A manufacturing method for forming a low concentration region atthe outermost portion of the repeating structure through high energy ionimplantations of multiple stages in an STM structure is described indetail as the thirty-sixth embodiment in reference to FIGS. 129 to 136.

[0551] The manufacturing method of the present embodiment first followsthe process shown in FIGS. 70 to 72. Thereby, a plurality of trenches 23is created and phosphorous ion implanted regions 3 and boron ionimplanted regions 4 are formed in the sidewalls of the respectivetrenches 23.

[0552] After this, in reference to FIG. 129, a film 41 q, such as asilicon oxide film, is formed by means of a CVD method so as to fill inall trenches 23 according to a conventional method. The process up tothis point is the same as a method shown in the other above describedembodiments. After this, though the respective implanted regions 3 and 4may be diffused from the sidewalls of trenches 23 by carrying out a heattreatment, a heat treatment is not carried out on this example.

[0553] In reference to FIG. 130, a resist pattern 31 v having apredetermined pattern is formed on film 41 q by means of photomechanicaltechnology. Ion implantation of phosphorus ions is carried out at a highenergy level by using this resist pattern 31 v as a mask and, thereby,phosphorous ion implanted regions 3 a are formed at deep locations ofthe outermost portion of the pn-repeating structure or of a region onestage before the outermost portion.

[0554] Here, though in FIG. 130, a case is described wherein ions areimplanted through thick buried film 41 q by using resist pattern 31 v asa mask, ions can, if necessary, be implanted after film 41 q is etchedor resist pattern 31 v can also be removed so that ions are implanted byusing only the pattern of film 41 q as a mask.

[0555] In reference to FIG. 131, ion implantation of phosphorus ions iscarried out at a middle energy level by using the above described resistpattern 31 v as a mask and, thereby, phosphorous ion implanted regions 3a are formed at locations of a middle depth of the outermost portion ofthe pn-repeating structure or of a region one stage before the outermostportion.

[0556] In reference to FIG. 132, ion implantation of phosphorus ions iscarried out at a low energy level by using the above described resistpattern 31 v as a mask and, thereby, phosphorous ion implanted regions 3a are formed at shallow locations of the outermost portion of thepn-repeating structure or of a region one stage before the outermostportion. After this, resist pattern 31 v is removed by means of, forexample, ashing.

[0557] The implantation concentration of phosphorus ions that areimplanted in the outermost portion of the pn-repeating structure or in aregion one stage before the outermost portion in the steps of FIGS. 130to 132 is approximately half of the implantation concentration ofphosphorus ions that have been implanted in the center portion.

[0558] Here, the order of the respective implantations, which are theabove described implantation to a deep location (FIG. 130), theimplantation to a location of a middle depth (FIG. 131) and theimplantation to a shallow location (FIG. 132), can be switched.Furthermore, the process of phosphorus ion implantation into theoutermost portion of the pn-repeating structure or into a region onestage before the outermost portion can be switched as a whole with theabove described implantation process of boron ions or phosphorus ionsinto the center portion.

[0559] Here, though in this example implantations at energy levels ofthree stages are described, ion may be implanted in two stages or in onestage in the case that an element of a class wherein withstand voltageis low has a thin epitaxial layer and, contrarily, in some cases ionsare implanted in four, or more, stages in the case that an element of aclass wherein withstand voltage is high has a thick epitaxial layer.Therefore, the present embodiment is not limited to having three stages.

[0560] In reference to FIG. 133, resist pattern 31 w, having apredetermined pattern, is formed on film 41 q by means ofphotomechanical technology. Ion implantation of boron ions is carriedout at a high energy level using this resist pattern 31 w as a mask and,thereby, boron ion implanted regions 4 a are formed at deep locations ofthe outermost portion in the pn-repeating structure or a region onestage before the outermost portion.

[0561] Here, though a case wherein ions are implanted through thickburied film 41 q by using resist pattern 31 w as a mask is described inreference to FIG. 133, ions can be implanted after film 41 q is etchedor ions can be implanted after resist pattern 31 w is also removed sothat only the pattern of film 41 q is used as a mask, if necessary.

[0562] In reference to FIG. 134, ion implantation of boron ions iscarried out at a middle energy level by using the above described resistpattern 31 w as a mask and, thereby, boron ion implanted regions 4 a areformed at locations of a middle depth of the outermost portion of thepn-repeating structure or of a region one stage before the outermostportion.

[0563] In reference to FIG. 135, ion implantation of boron ions iscarried out at a low energy level by using the above described resistpattern 31 w as a mask and, thereby, boron ion implanted regions 3 a areformed at shallow locations of the outermost portion of the pn-repeatingstructure or of a region one stage before the outermost portion. Afterthis, resist pattern 31 w is removed by means of, for example, ashing.

[0564] The implantation concentration of boron ions that are implantedin the outermost portion of the pn-repeating structure or in a regionone stage before the outermost portion in the steps of FIGS. 133 to 135is approximately half of the implantation concentration of boron ionsthat have been implanted in the center portion.

[0565] Here, the order of the respective implantations, which are theabove described implantation to a deep location (FIG. 133), theimplantation to a location of a middle depth (FIG. 134) and theimplantation to a shallow location (FIG. 135), can be switched.Furthermore, the process of boron ion implantation for giving a lowconcentration into the outermost portion of the pn-repeating structureor into a region one stage before the outermost portion can be switchedas a whole with the above described implantation process of boron ionsor phosphorus ions for giving a high concentration into the centerportion or implantation process of phosphorus ions for giving a lowconcentration into the outermost portion of the pn-repeating structureor into a region one stage before the outermost portion.

[0566] Here, these processes are not limited to the ion implantationsfor lowering the concentration in three stages and the number of stagesmay be greater or smaller than this in the same manner in the abovedescribed phosphorous ion implanted regions 3 a.

[0567] Though in the present embodiment a case wherein only one columnof a pn combination made of a p layer and an n layer of a lowconcentration is formed at the outermost portion of the pn-repeatingstructure is cited as an example for the purpose of simplification, thenumber of columns is not limited to this.

[0568] In reference to FIG. 136, a heat treatment is carried out and,thereby, the respective impurities of a plurality of boron ion implantedregions 4 a and a plurality of phosphorous ion implanted regions 3 aaligned in the depth direction of the semiconductor substrate arediffused into the surrounding areas so as to be integrated and, then,p-type impurity regions 4 and n-type drift regions 3 forming thepn-repeating structure are formed. After this, MOS-FET formationportions, electrodes, and the like, are formed.

[0569] Here, though in FIG. 136, the connected n-type drift regions 3and p-type impurity regions 4 are represented in two stages of a lowconcentration and of a high concentration for the purpose ofsimplification, in actuality, the concentration changes without discretestages and in a continuous manner. In addition, though the p-typeimpurity region 4 of a low concentration at the outermost portion of thepn-repeating structure has a wavy cross sectional form that spreadssomewhat to the outer periphery in a portion having a high impurityconcentration, this detail is omitted for the purpose of simplification.

[0570] (Thirty-Seventh Embodiment)

[0571] A manufacturing method in the case that high energy ionimplantation is carried out in multiple stages at the time when theconcentration is lowered at the outermost portion of the pn repeatingstructure in an STM structure and in the case that a p-type impurityregion is located at the outermost portion of the pn-repeating structureis described in detail as the thirty-seventh embodiment in reference toFIGS. 137 to 140.

[0572] The manufacturing method of the present embodiment, first,follows the steps shown in FIGS. 70 to 72 and, after that, follows theadditional steps of FIGS. 129 to 132. Thereby, a plurality of trenches23, phosphorous ion implanted regions 3 and boron ion implanted regions4 formed in the sidewalls on both sides of respective trenches 23, afilm 41 q filling in respective trenches 23 and a phosphorus ionimplanted region 3 a located one stage before the outermost portion ofthe pn-repeating structure are formed.

[0573] In reference to FIG. 137, a resist pattern 31 x having apredetermined pattern is formed on film 41 q by means of photomechanicaltechnology. Ion implantation of boron ions is carried out at a highenergy level using this resist pattern 31 x as a mask and, thereby, aboron ion implanted region 4 a is formed at a deep location in a regionthat becomes the outermost portion of the pn-repeating structure.

[0574] Here, though a case is described in reference to FIG. 137 whereinions are implanted through thick buried film 41 q using resist pattern31 x as a mask, ions can be implanted after film 41 q is etched or ionscan be implanted after removing resist pattern 31 x so that only thepattern of film 41 q is used as a mask.

[0575] In reference to FIG. 138, ion implantation of boron ions iscarried out at a middle energy level using the above described resistpattern 31 x as a mask and, thereby, a boron ion implanted region 4 a isformed at a location of a middle depth in a region that becomes theoutermost portion of the pn-repeating structure.

[0576] In reference to FIG. 139, ion implantation of boron ions iscarried out at a low energy level using the above described resistpattern 31 x as a mask and, thereby, a boron ion implanted region 4 a isformed at a shallow location in a region that becomes the outermostportion of the pn-repeating structure. After this, resist pattern 31 xis removed by means of, for example, ashing.

[0577] The implantation concentration of boron ions implanted in theoutermost portion of the pn-repeating structure in the steps of FIGS.137 to 139 is set at approximately half the implantation concentrationof boron ions implanted into the center portion.

[0578] Here, the order of the respective implantations, which are theabove described implantation into a deep location (FIG. 137),implantation into a middle location (FIG. 138) and implantation into ashallow location (FIG. 139), can be switched. Furthermore, theseimplantation steps of boron ions of a low concentration into theoutermost portion can be switched as a whole with the above describedimplantation steps of boron ions or phosphorus ions of a highconcentration into the center portion or with the implantation steps ofphosphorus ions of a low concentration into a region one stage closer tothe center portion from the outermost portion of the pn-repeatingstructure.

[0579] Here, these steps are not limited to the ion implantations inthree stages but, rather, the number of ion implantations may be greaterthan, or fewer than, this in the same manner as in the above describedion implantations into phosphorus ion implanted region 3 a.

[0580] Though in the present embodiment, a case wherein only one columnof a pn combination made of a p layer and an n layer of a lowconcentration is formed at the outermost portion of the pn-repeatingstructure is cited as an example for the purpose of simplification, theinvention is not specifically limited to this.

[0581] In reference to FIG. 140, a heat treatment is carried out and,thereby, the plurality of boron ion implanted regions 4 a and theplurality of phosphorous ion implanted regions 3 a aligned in the depthdirection of the semiconductor substrate, respectively, are diffusedinto the surrounding areas so as to be integrated and, thereby, p-typeimpurity region 4 and n-type drift region 3 forming the pn-repeatingstructure are formed. After this, MOS-FET configuration portions,electrodes, and the like, are formed.

[0582] Here, though the connected n-type drift regions 3 and p-typeimpurity regions 4 are represented in FIG. 140 as having two stages, ofa low concentration and a high concentration for the purpose ofsimplification, in actuality the concentration changes without discretestages and in a continuous manner. In addition, though p-type impurityregion 4 of a low concentration at the outermost portion of thepn-repeating structure has a wavy cross sectional form that spreadssomewhat to the outer periphery in a portion having a high impurityconcentration, the detailed description of this is omitted for thepurpose of simplification.

[0583] (Thirty-Eighth to Fortieth Embodiments)

[0584] Configurations wherein an active element is not formed at theoutermost portion of the pn-repeating structure are shown as thethirty-eighth to fortieth embodiments in FIGS. 141 to 143.

[0585] In reference to FIG. 141, the configuration of the thirty-eighthembodiment shares with the configuration of FIG. 3 the point that theconcentration is lowered in only one pair (one stage) made up of p-typeimpurity region 4 and n-type drift region 3 at the outermost portion, onboth the left and right sides, of the pn-repeating structure and differsfrom the configuration of FIG. 3 in the point that a MOS-FET, which isan active element, is not formed above the regions wherein theconcentration is lowered in the present embodiment.

[0586] p-type impurity regions 5 are formed above p-type impurityregions 4 and n-type drift regions 3 of a low concentration at theoutermost portions of the pn-repeating structure and are electricallyconnected to source electrodes 10 while n⁺ source regions 6 and gateelectrodes 9, which are components of MOS-FETs, are not formed in thepresent embodiment.

[0587] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 3 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0588] In reference to FIG. 142, the configuration of the thirty-ninthembodiment shares with the configuration of FIG. 87 the point that theconcentration is lowered in only one pair (one stage) made of p-typeimpurity region 4 and n-type drift region 3 at the outermost portion ofthe pn-repeating structure in the STM having a structure wherein gatesare parallel to trenches and differs from the configuration of FIG. 87in the point that a MOS-FET, which is an active element, is not formedabove the region wherein the concentration is lowered in the presentembodiment.

[0589] p-type impurity regions 21 are formed above p-type impurityregions 4 and n-type drift regions 3 of a low concentration at theoutermost portions of the pn-repeating structure and are electricallyconnected to source electrodes 10 while n⁺ source regions 6 and gateelectrodes 9, which are components of MOS-FETs, are not formed in thepresent embodiment.

[0590] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 87 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0591] In reference to FIG. 143, the configuration of the fortiethembodiment shares with the configuration of FIG. 6 the point that theconcentration is lowered in only p-type impurity region 4 at outermostportion of the pn-repeating structure in the buried multi-layerepitaxial structure and differs from the configuration of FIG. 6 in thepoint that a MOS-FET, which is an active element, is not formed abovethe region wherein the concentration is lowered.

[0592] p-type impurity regions 5 are formed above p-type impurityregions 4 of a low concentration at the outermost portions of thepn-repeating structure and are electrically connected to sourceelectrodes 10 while n⁺ source regions 6 and gate electrodes 9, which arecomponents of MOS-FETs, are not formed in the present embodiment.

[0593] Here, the other parts of the configuration are approximately thesame as the configuration shown in FIG. 6 and, therefore, the samesymbols are attached to the same members, of which the descriptions areomitted.

[0594] (Forty-First Embodiment)

[0595] A configuration wherein the concentration is lowered at theoutermost portion of the pn-repeating structure of a horizontal powerMOS-FET mounted on an SOI (Silicon On Insulator) substrate is describedin detail as the forty-first embodiment in reference to FIGS. 144 and145.

[0596] In reference to FIGS. 144 and 145, a semiconductor layer 60 isformed above a silicon substrate 51 via an insulating film 52, such as asilicon oxide film. Then, a horizontal power MOS-FET having apn-repeating structure, wherein the concentration is lowered at theoutermost portion, is formed according to the present invention.

[0597] p-type impurity regions 4 and n-type impurity regions 3 areformed in alternation so as to form a pn-repeating structure in thissemiconductor layer 60. Then, the concentration is lowered in two stagesat the outermost portion of this pn-repeating structure having one pairmade up of a pn combination as one unit, as shown in FIG. 145.

[0598] Here, p-type region 5 is formed so as to form a pn junction withn-type impurity regions 3 and so as to be electrically connected top-type impurity regions 4. In addition, n⁺ source regions 6 are formedso that portions of p-type region 5 are placed between n⁺ source regions6 and n-type impurity regions 3. A gate electrode layer 9 is formed soas to face p-type region 5 placed between n-type impurity regions 3 andn⁺ source regions 6 via a gate insulating layer 8. This gate electrodelayer 9 extends in the direction of pn repetition above the first mainsurface.

[0599] An n⁺ region 54 and an nb region 53 are formed on the sideopposite to p-type region 5 of the pn-repeating structure and n⁺ region54 is electrically connected to a drain electrode.

[0600] Here, trenches may be provided between p-type impurity regions 4and n-type impurity regions 3 in the above described pn-repeatingstructure and, in this case, trenches 23 filled in with insulators 24,or the like, are located between p-type impurity regions 4 and n-typeimpurity regions 3, as shown in FIGS. 146 and 147.

[0601] (Forty-Second Embodiment)

[0602] In the above described twenty-third, twenty-eighth andthirty-fourth embodiments, the region wherein the concentration islowered at the outermost portion of the pn-repeating structure is formedby carrying out a counter ion implantation (counter doping) in thesidewalls of the trench located at the edge portion of the repeatingstructure. In contrast to this, impurities of the same conductive typeas the impurities that have already been implanted into the sidewalls ofthe trenches located in the center portion of the pn-repeating structureare additionally implanted and, thereby, the concentrations of p layers4 and n layers 3 of the pn-repeating structure in the center portion areenhanced so that the concentration of the impurity region in thesidewall of the trench at the outermost portion of the repeatingstructure may become relatively low. In the following, this isconcretely described.

[0603] In the twenty-third embodiment, first, p-type impurity regions 4and n-type impurity regions 3 of a comparatively low concentration areformed in the sidewalls of trenches 23 by following the steps of FIGS.79 to 81. After this, the filling within trenches 23 in the centerportion of pn-repeating structure is removed. Then, additional p-typeimpurities are implanted into p-type impurity regions 4 in the sidewallson one side of these trenches 23 in the center portion and additionaln-type impurities are implanted into n-type impurity regions 3 in thesidewalls on the other side. Thereby, the concentrations of p-typeimpurity regions 4 and n-type impurity regions 3 in the sidewalls oftrenches 23 in the center portion of the repeating structure areenhanced so that impurity regions 3 and 4 in the sidewalls of trench 23at the outermost portion of the repeating structure become relativelylow concentration regions.

[0604] In addition, in the twenty-eighth embodiment, first, p-typeimpurity regions 4 and n-type impurity regions 3 of a comparatively lowconcentration are formed in the sidewalls of trenches 23 by followingthe steps of FIGS. 106 to 110. After this, the filling within trenches23 in the center portion of pn-repeating structure is removed. Then,additional p-type impurities are implanted in p-type impurity regions 4in the sidewalls on both sides of trenches 23 in this center portion andadditional n-type impurities are implanted into n-type impurity regions3 in the sidewalls on both sides of other trenches 23 in the centerportion. Thereby, the concentrations of p-type impurity regions 4 andn-type impurity regions 3 in the sidewalls of trenches 23 in the centerportion of the repeating structure are enhanced so that impurity regions3 and 4 in the sidewalls of trench 23 at the outermost portion of therepeating structure become relatively low concentration regions.

[0605] In addition, in the thirty-fourth embodiment, first, p-typeimpurity regions and n-type impurity regions 3 of a comparatively lowconcentration are formed in the sidewalls of trenches 23 by followingthe steps of FIGS. 120 to 123. After this, the filling within trenches23 in the center portion of pn-repeating structure is removed. Then,additional p-type impurities are implanted in p-type impurity regions 4in the sidewalls on both sides of trenches 23 in this center portion andadditional n-type impurities are implanted into n-type impurity regions3 in the sidewalls on both sides of other trenches 23 in the centerportion. Thereby, the concentrations of p-type impurity regions 4 andn-type impurity regions 3 in the sidewalls of trenches 23 in the centerportion of the repeating structure are enhanced so that impurity regions3 and 4 in the sidewalls of trench 23 at the outermost portion of therepeating structure become relatively low concentration regions.

[0606] Here, though in the above described second to forty-secondembodiments, a case is described wherein the concentration of theimpurity region located at the outermost portion of the pn-repeatingstructure is lower than that in the center portion, the same effect canbe obtained by setting the general effective charge amount of theimpurity region located at the outermost portion of the-pn-repeatingstructure to be smaller than that in the center portion, as described inthe first embodiment.

[0607] (Effects of the Invention)

[0608] By using the present invention the main withstanding voltage of apower semiconductor device wherein a three-dimensional multiple RESURFprinciple with an element withstand voltage in a broad range of 20 V to6000 V is specifically applied can be improved and the tradeoffrelationship between the main withstanding voltage and the ON resistancecan also be improved so that an inexpensive semiconductor device havinga low power loss and having a small chip size can be obtained.

[0609] In addition, by using trenches of a DLT structure andmanufacturing method corresponding to these, a semiconductor devicehaving a good yield can be obtained at a lower cost.

[0610] Here, the embodiments disclosed herein should be considered to beillustrative from all points of view and are not limitative. The scopeof the present invention is not defined by the above description but,rather, is defined by the claims and is intended to include meaningsequivalent to the claims and all modifications within the scope.

Industrial Applicability

[0611] The present invention can be advantageously applied to a powersemiconductor device and a manufacturing method for the same wherein athree-dimensional multiple RESURF principle with a element withstandvoltage in a broad range of 20 V to 6000 V is specifically applied.

1. A semiconductor device having a repeating structure wherein astructure where a first impurity region (3) of a first conductive typeand a second impurity region (4) of a second conductive type are alignedside by side is repeated twice, or more, in a semiconductor substrate ofthe first conductive type, wherein the semiconductor device ischaracterized in that a low concentration region (3, 4) that is eithersaid first or second impurity region (3, 4) located at the outermostportion of said repeating structure has the lowest impurityconcentration or has the least generally effective charge amount fromamong all of said first and second impurity regions (3, 4) forming saidrepeating structure.
 2. The semiconductor device according to claim 1,characterized in that the impurity concentration of said lowconcentration region (3, 4) is no lower than 30% and no higher than 70%of the impurity concentration of a high concentration region (3, 4) thatis either said first or second impurity region (3, 4) located closer tothe center portion of said repeating structure than is said lowerconcentration region (3, 4).
 3. The semiconductor device according toclaim 2, characterized in that the impurity concentration of a middleconcentration region (3, 4) that is either said first or second impurityregions (3, 4) located between said low concentration region (3, 4) andsaid high concentration region (3, 4) is higher than the impurityconcentration of said low concentration region (3, 4) and is lower thanthe impurity concentration of said high concentration region (3, 4). 4.The semiconductor device according to claim 1, characterized in thatsaid semiconductor substrate has a first main surface and a second mainsurface facing each other, a third impurity region (5) of the secondconductive type is formed at least at a portion on said first mainsurface side in at least one of said plurality of first impurity regions(3) forming said repeating structure so as to form a main pn junctionwith said first impurity regions (3), and a fourth impurity region (1)of the first conductive type is formed on said second main surface sideof said repeating structure.
 5. The semiconductor device according toclaim 1, characterized in that said third impurity region (5) forming amain pn junction with said first impurity region (3) is a body region ofan insulating gate type field effect transistor portion.
 6. Thesemiconductor device according to claim 1, characterized in that saidlow concentration region (3, 4) located at the outermost portion of therepeating structure does not form an active element.
 7. Thesemiconductor device according to claim 1, further comprising: a thirdimpurity region (5) of the second conductive type that is formed atleast in a portion of an upper portion in the vicinity of an edge ofsaid first impurity region (3) extending in one specific direction; afourth impurity region (54) of the first conductive type that is formedin at least a portion of an upper portion in the vicinity of an edge ofsaid first impurity region (3) in the direction opposite to said onespecific direction; a first electrode electrically connected to saidthird impurity region (5); and a second electrode electrically connectedto said fourth impurity region (54), wherein the semiconductor device ischaracterized in that said first and second electrodes are both formedon said first main surface.
 8. The semiconductor device according toclaim 1, characterized in that said semiconductor substrate has a firstmain surface and a second main surface facing each other and has aplurality of trenches (23) in said first main surface, and saidrepeating structure has a structure wherein a structure where said firstand second impurity regions (3, 4) is aligned with said trench (23)located in between is repeated twice or more.
 9. The semiconductordevice according to claim 8, characterized in that the impurityconcentration of said low concentration region (3, 4) is no lower than30% and no higher than 70% of the impurity concentration of a highconcentration region (3, 4) that is either said first or second impurityregion (3, 4) located closer to the center portion in said repeatingstructure than said low concentration region (3, 4).
 10. Thesemiconductor device according to claim 9, characterized in that theimpurity concentration of a middle concentration region (3, 4) that iseither said first or second impurity region (3, 4) located between saidlow concentration region (3, 4) and said high concentration region (3,4) is higher than the impurity concentration of said low concentrationregion (3, 4) and is lower than the impurity concentration of said highconcentration region (3, 4).
 11. The semiconductor device according toclaim 8, characterized in that said first impurity region (3) is formedon one side of a mesa portion of said semiconductor substrate surroundedby said plurality of trenches (23), said second impurity region (4) isformed on the opposite side of the mesa portion and a third impurityregion (5) of the second conductive type is formed in at least a portionon said first main surface side of said first impurity region (3) so asto form a main pn junction with said first impurity region (3).
 12. Thesemiconductor device according to claim 11, characterized in that saidthird impurity region (5) forming the main pn junction with said firstimpurity region (3) is a body region of an insulating gate-type fieldeffect transistor portion.
 13. The semiconductor device according toclaim 8, characterized in that said low concentration region (3, 4)located at the outermost portion of the repeating structure does notform an active element.
 14. The semiconductor device according to claim8, characterized in that a trench (23) located at the outermost portionof said plurality of trenches (23) is a first trench of a dotted lineform having a surface pattern of a dotted line form wherein a pluralityof first holes (23 a) is arranged at intervals in a predetermineddirection in said first main surface and said low concentration region(3, 4) is formed so as to be located on one of the sidewalls of saidfirst trench (23) of a dotted line form.
 15. The semiconductor deviceaccording to claim 14, characterized in that the sum of the lengths ofthe sidewalls on one side of said plurality of first holes (23 a) thatform said first trench (23) of a dotted line form in said first mainsurface is no less than 30% and no greater than 70% of the length of thesidewall on one side of a continuously extending trench (23) locatedcloser to the center portion than is said first trench (23) of a dottedline form in said first main surface.
 16. The semiconductor deviceaccording to claim 14, characterized in that a trench located betweensaid first trench (23) of the doted line form and said continuouslyextending trench (23) is a second trench (23) of a dotted line formhaving a surface pattern of a dotted line form wherein a plurality ofsecond holes (23 a ₁, 23 a ₂) is arranged at intervals in apredetermined direction in said first main surface, and the sum of thelengths of the sidewalls on one side of said plurality of second holes(23 a ₁, 23 a ₂) forming said second trench (23) of a dotted line formin said first main surface is greater than the sum of the lengths of thesidewalls on one side of said plurality of first holes (23 a ₃) formingsaid first trench (23) of a dotted line form in said first main surfaceand is smaller than the length of the sidewall on one side of acontinuously extending trench (23) located closer to the center portionthan is said second trench (23) of a dotted line form in said first mainsurface.
 17. The semiconductor device according to claim 14,characterized in that said first impurity region (3) is formed on oneside of the mesa portion of said semiconductor substrate surrounded bysaid plurality of trenches (23), said second impurity region is formedon the opposite side of the mesa portion and a third impurity region (5)of the second conductive type is formed in at least a portion on saidfirst main surface side of said first impurity region (3) so as to forma main pn junction with said first impurity region (3).
 18. Thesemiconductor device according to claim 17, characterized in that saidthird impurity region (5) forming the main pn junction with said firstimpurity region (3) is a body region of an insulating gate-type fieldeffect transistor portion.
 19. The semiconductor device according toclaim 14, characterized in that said low concentration region (3, 4)located at the outermost portion of the repeating structure does notform an active element.
 20. The semiconductor device according to claim1, characterized in that said semiconductor substrate has a first mainsurface and a second main surface facing each other and has a pluralityof trenches including first and second trenches (23) adjoining eachother in said first main surface, and a structure where said firstimpurity region (3) is formed on each of the two sidewalls of said firsttrench (23) and said second impurity region (4) is formed on each of thetwo sidewalls of said second trench (23) is repeated twice or more. 21.The semiconductor device according to claim 20, characterized in thatthe impurity concentration of said low concentration region (3, 4) is nolower than 30% and no higher than 70% of the impurity concentration of ahigh concentration region (3, 4) that is either said first or secondimpurity region (3, 4) located closer to the center portion of saidrepeating structure than is said lower concentration region (3, 4). 22.The semiconductor device according to claim 21, characterized in thatthe impurity concentration of a middle concentration region (3, 4) thatis either said first or second impurity region (3, 4) located betweensaid low concentration region (3, 4) and said high concentration region(3, 4) is higher than the impurity concentration of said lowconcentration region (3, 4) and is lower than the impurity concentrationof said high concentration region (3, 4).
 23. The semiconductor deviceaccording to claim 20, characterized in that said first impurity region(3) is formed on one side of the mesa portion of said semiconductorsubstrate surrounded by said plurality of trenches (23), said secondimpurity region (4) is formed on the opposite side of the mesa portionand a third impurity region (5) of the second conductive type is formedin at least a portion on said first main surface side of said firstimpurity region (3) so as to form a main pn junction with said firstimpurity region (3).
 24. The semiconductor device according to claim 23,characterized in that said third impurity region (5) forming a main pnjunction with said first impurity region (3) is a body region of aninsulating gate-type field effect transistor portion.
 25. Thesemiconductor device according to claim 20, characterized in that saidlow concentration region (3, 4) located at the outermost portion of therepeating structure does not form an active element.
 26. Thesemiconductor device according to claim 20, characterized in that thetrench (23) located at the outermost portion of said plurality oftrenches (23) is a first trench (23) of a dotted line form having asurface pattern of a dotted line form wherein said plurality of firstholes (23 a) is arranged at intervals in a predetermined direction insaid first main surface and said low concentration region (3, 4) isformed so as to be located in a sidewall on⁻ one side of said firsttrench (23) of a dotted line form.
 27. The semiconductor deviceaccording to claim 26, characterized in that the sum of the lengths ofthe sidewalls on one side of said plurality of first holes (23 a)forming said first trench (23) of a dotted line form in said first mainsurface is no less than 30% and no greater than 70% of the length of asidewall on one side of a trench (23) continuously extending locatedcloser to the center portion than said first trench (23) of a dottedline form in said first main surface.
 28. The semiconductor deviceaccording to claim 26, characterized in that a trench (23) locatedbetween said first trench (23) of a dotted line form and saidcontinuously extending trench (23) is a second trench (23) of a dottedline form having a surface pattern of a dotted line form wherein aplurality of second holes (23 a ₁, 23 a ₂) is arranged at intervals in apredetermined direction in said first main surface, and the sum of thelengths of the sidewalls on one side of said plurality of second holes(23 a ₁, 23 a ₂) forming said second trench (23) of a dotted line formin said first main surface is greater than the sum of the lengths of thesidewalls on one side of said plurality of first holes (23 a ₃) formingsaid first trench (23) of a dotted line form in said first main surfaceand is smaller than the length of the sidewall on one side of thecontinuously extending trench (23) located closer to the center portionthan said second trench (23) of a dotted line form in said first mainsurface.
 29. The semiconductor device according to claim 26,characterized in that said first impurity region (3) is formed on oneside of the mesa portion of said semiconductor substrate surrounded bysaid plurality of trenches (23), said second impurity region is formedon the opposite side of the mesa portion and a third impurity region (5)of the second conductive type is formed in at least a portion on saidfirst main surface side of said first impurity region (3) so as to forma main pn junction with said first impurity region (3).
 30. Thesemiconductor device according to claim 26, characterized in that saidthird impurity region (5) forming the main pn junction with said firstimpurity region (3) is a body region of an insulating gate-type fieldeffect transistor portion.
 31. The semiconductor device according toclaim 26, characterized in that said low concentration region (3, 4)located at the outermost portion of the repeating structure does notform an active element.
 32. A manufacturing method for a semiconductordevice having a structure wherein a structure where a first impurityregion (3) of a first conductive type and a second impurity region (4)of a second conductive type are aligned side by side is repeated twiceor more in a semiconductor substrate of the first conductive type,characterized in that a low concentration region (3, 4) that is eithersaid first or second impurity region (3, 4) located at the outermostportion of said repeating structure and said first and second impurityregions (3, 4), other than the low concentration region, are formed soas to have independently changed concentrations so that said lowconcentration region (3, 4) has the lowest impurity concentration or hasthe least generally effective charge amount among all of said first andsecond impurity regions (3, 4) forming said repeating structure.
 33. Themanufacturing method for a semiconductor device according to claim 32,characterized in that said low concentration region (3, 4) and saidother first and second impurity-regions (3, 4) are formed by means ofion implantation and heat treatment wherein the concentrations have beenindependently changed in order to form said low concentration region (3,4) and said other first and second impurity regions (3, 4) of which theconcentrations have been independently changed.
 34. The manufacturingmethod for a semiconductor device according to claim 32, characterizedin that said low concentration region (3, 4) and said other first andsecond impurity regions (3, 4) are formed by means of ion implantationand multi-stage epitaxial growth wherein the concentrations have beenindependently changed in order to form said low concentration region (3,4) and said other first and second impurity regions (3, 4) of which theconcentrations have been independently changed.
 35. The manufacturingmethod for a semiconductor device according to claim 32, characterizedin that said low concentration region (3, 4) and said other first andsecond impurity regions (3, 4) are formed by means of ion implantationwherein the concentrations have been independently changed and theimplantation energies have been changed according to multiple levels inorder to form said low concentration region (3, 4) and said other firstand second impurity regions (3, 4) of which the concentrations have beenindependently changed.
 36. The manufacturing method for a semiconductordevice according to claim 32, characterized in that said other first andsecond impurity regions (3, 4) are formed of impurity ions implantedthrough first openings of a mask (31 q) for ion implantation and saidlow concentration region (3, 4) is formed of impurity ions implantedthrough second openings of which the total opening area is smaller thanthat of said first openings in order to form said low concentrationregion (3, 4) and said other first and second impurity regions (3, 4) ofwhich the concentrations have been independently changed.
 37. Themanufacturing method for a semiconductor device according to claim 36,characterized in that said second openings have a configuration whereina plurality of microscopic openings separated from each other aredensely arranged, and impurity ions implanted through all of saidplurality of microscopic openings are integrated by carrying out a heattreatment so as to form said low concentration region (3, 4) of whichthe finished average impurity concentration is lower than that of saidother first and second impurity regions (3, 4).
 38. The manufacturingmethod for a semiconductor device according to claim 32, characterizedby further comprising the steps of simultaneously forming one, or more,trench(es) (23) and a trench (23) of a dotted line form that is locatedalong the outside of said one, or more, trench(es) (23) wherein aplurality of first holes (23 a) is arranged at intervals in apredetermined direction and that, thereby, has a surface pattern of adotted line form in said first main surface; and simultaneously formingsaid low concentration region (3, 4) in the sidewall on one side of saidtrench (23) of a dotted line form and said other first and secondimpurity regions (3, 4) in the sidewalls on one side of said one, ormore, trenches (23) by simultaneously carrying out an ion implantationin the sidewalls on one side of the respective trenches of said one, ormore, trench (23) and said trench (23) of a dotted line form.
 39. Themanufacturing method for a semiconductor device according to claim 32,characterized by further comprising the steps of: creating two, or more,trenches (23) in the first main surface of said semiconductor substrate;ion implantation of impurities into the sidewalls on one side of saidtwo, or more, trenches (23) in order to form said first or secondimpurity regions (3, 4); and forming said low concentration region (3,4) by carrying out an ion implantation of impurities of a conductivetype opposite to that of the already implanted impurities in thesidewall on one side of said trench (23) located at the outermostportion under the condition wherein said two, or more, trenches (23)except the trench (23) located at the outermost portion are filled inwith a filling layer so that the concentration of the already implantedimpurities is substantially lowered.
 40. The manufacturing method for asemiconductor device according to claim 32, characterized by furthercomprising the steps of: creating one, or more, trench(es) (23) in afirst main surface of said semiconductor substrate; ion implantation ofa first implantation amount for forming said first or second impurityregion (3, 4) in the sidewalls on one side of said one, or more,trenches (23); creating a new trench (23) at the outermost portionoutside of said one, or more, trench(es) (23) under the conditionwherein each of said one, or more, trench(es) (23) is filled in with afilling layer; and ion implantation of a second implantation amount thatis smaller than said first implantation amount for forming said lowconcentration region (3, 4) in the sidewall on one side of said trench(23) at the outermost portion.
 41. The manufacturing method for asemiconductor device according to claim 32, characterized by furthercomprising the steps of: simultaneously creating two, or more, trenches(23) including first and second trenches (23) adjoining each other in afirst main surface of said semiconductor substrate and a trench (23) ofa dotted line form having a surface pattern of a dotted line form insaid first main surface by arranging a plurality of first holes (23 a)at intervals in a predetermined direction so as to be located along theoutside of said two, or more, trenches (23); ion implantation of firstimpurities for forming said first impurity region (3) in each of thesidewalls on both sides of said first trench (23); and ion implantationof second impurities for forming said second impurity region (4) in eachof the sidewalls on both sides of said second trench (23), wherein saidlow concentration regions (3, 4) are created in the sidewalls on bothsides of said trench (23) of a dotted line through implantation at thesame time of the ion implantation of said first or second impurities.42. The manufacturing method for a semiconductor device according toclaim 32, characterized by further comprising the steps of: creating afirst group of trenches made of a plurality of first trenches (23) in afirst main surface of said semiconductor substrate; ion implantationinto each of the sidewalls on both sides of said first trenches (23) forforming said first impurity regions (3); creating a second group oftrenches made of a plurality of second trenches (23) in said first mainsurface so that said first trenches (23) and said second trenches (23)are positioned in an alternating manner; ion implantation in each of thesidewalls on both sides of said second trenches (23) for forming saidsecond impurity regions (4); implanting ions of a conductive typeopposite to that of the already implanted impurities in the sidewalls onboth sides of said trench (23) located at the outermost portion underthe condition wherein said first and second trenches (23) arranged in analternating manner except the trench (23) located at the outermostportion are filled in with a filling layer so as to form said lowconcentration regions (3, 4) by substantially lowering the concentrationof the already implanted impurities.
 43. The manufacturing method for asemiconductor device according to claim 32, characterized by furthercomprising the steps of: creating a first group of trenches made of aplurality of first trenches (23) in a first main surface of saidsemiconductor substrate; ion implantation for forming said firstimpurity regions (3) in the sidewalls on both sides of each of saidfirst trenches (23); creating a second group of trenches made of aplurality of second trenches (23) in said first main surface in thecondition that each of said first trenches (23) is filled in with afilling layer so that said first trenches (23) and said second trenches(23) are alternately located; ion implantation for forming said secondimpurity regions (4) in the sidewalls on both sides of each of saidsecond trenches (23); creating a new trench (23) at the outermostportion outside of the trench (23) located at the outermost portion ofsaid first and second trenches (23) that are arranged in an alternatingmanner under the condition wherein each of said first and secondtrenches (23) is filled in with a filling layer; and forming said lowconcentration region (3, 4) of which the impurity concentration is lowerthan that of said first or second impurity regions (3, 4) by implantingimpurity ions of said first or second conductive type into the sidewallson both sides of said trench (23) at the outermost portion.
 44. Themanufacturing method for a semiconductor device according to claim 32,characterized by further comprising the steps of: simultaneouslycreating a first group of trenches made of a plurality of first trenches(23) and a second group of trenches made of a plurality of secondtrenches (23) in a first main surface of said semiconductor substrate sothat said first trenches (23) and said second trenches (23) arealternately located; ion implantation for forming said first impurityregions (3) into the sidewalls on both sides of each of said pluralityof first trenches (23) forming said first group of trenches under acondition wherein said second group of trenches is filled in with afirst filling layer; ion implantation for forming said second impurityregions (4) into the sidewalls on both sides of each of said pluralityof second trenches (23) forming said second group of trenches under acondition wherein said first group of trenches is filled in with asecond filling layer; forming said low concentration regions (3, 4) byimplanting impurity ions of a conductive type opposite to that of thealready implanted impurities into the sidewalls on both sides of saidtrench (23) at the outermost portion so that the concentration of thealready implanted impurities is lowered under the condition wherein allthe trenches of said plurality of first trenches (23) forming said firstgroup of trenches and of said plurality of second trenches (23) formingsaid second group of trenches except the trench (23) at the outermostportion located in the outermost portion.
 45. The manufacturing methodfor a semiconductor device according to claim 32, characterized byfurther comprising the steps of: simultaneously creating a first groupof trenches made of a plurality of first trenches (23) and a secondgroup of trenches made of a plurality of second trenches (23) in a firstmain surface of said semiconductor substrate so that said first trenches(23) and said second trenches (23) are alternately located; ionimplantation for forming said first impurity regions (3) into thesidewalls on both sides of each of said plurality of first trenches (23)forming said first group of trenches under a condition wherein saidsecond group of trenches is filled in with a first filling layer; andion implantation for forming said second impurity regions (4) into thesidewalls on both sides of each of said plurality of second trenches(23) forming said second group of trenches under a condition whereinsaid first group of trenches is filled in with a second filling layer,wherein the trench (23) at the outermost portion located at theoutermost portion from among said plurality of first trenches (23)forming said first group of trenches and said plurality of secondtrenches (23) forming said second group of trenches is a trench (23) ofa dotted line form having a surface pattern of a dotted line formwherein a plurality of holes (23 a) is arranged at intervals in apredetermined direction in said first main surface.
 46. Themanufacturing method for a semiconductor device according to claim 32,characterized by further comprising the steps of: creating two, or more,trenches (23) in a first main surface of said semiconductor substrate;ion implantation of impurities into the sidewalls on one side of saidtwo, or more, trenches (23) for forming said first or second impurityregions (3, 4); and ion implantation of impurities of the sameconductive type as that of the already implanted impurities into thesidewalls on one side of the trenches (23) other than said trench (23)located at the outermost portion under the condition wherein the trench(23) located at the outermost portion from among said two, or more,trenches (23) is filled in with a filling layer and, thereby, theconcentration of the already implanted impurities is substantiallyincreased so that said first or second impurity region (3, 4) in thesidewall of said trench (23) located at the outermost portion becomes aregion of a comparatively low concentration.
 47. The manufacturingmethod for a semiconductor device according to claim 32, characterizedby further comprising the steps of: creating a first group of trenchesmade of a plurality of first trenches (23) in a first main surface ofsaid semiconductor substrate; ion implantation for forming said firstimpurity regions (3) in the sidewalls on both sides of each of saidfirst trenches; creating a second group of trenches made of a pluralityof second trenches (23) in said first main surface so that said firsttrenches (23) and said second trenches (23) are arranged in analternating manner; ion implantation for forming said second impurityregions (4) in the sidewalls on both sides of each of said secondtrenches (23); ion implantation of impurities of the same conductivetype as that of the already implanted impurities into the sidewalls onboth sides of the trenches (23) other than said trench (23) located atthe outermost portion under the condition wherein the trench (23)located at the outermost portion from among said first and secondtrenches (23) arranged in an alternating manner is filled in with afilling layer and, thereby, the concentration of the already implantedimpurities is substantially increased so that said first or secondimpurity region (3, 4) in the sidewall of said trench (23) located atthe outermost portion becomes a region of a comparatively lowconcentration.
 48. The manufacturing method for a semiconductor deviceaccording to claim 32, characterized by further comprising the steps of:simultaneously creating a first group of trenches made of a plurality offirst trenches (23) and a second group of trenches made of a pluralityof second trenches (23) in a first main surface of said semiconductorsubstrate so that said first trenches (23) and said second trenches (23)are alternately located; ion implantation for forming said firstimpurity regions (3) into the sidewalls on both sides of each of saidplurality of first trenches (23) forming said first group of trenchesunder a condition wherein said second group of trenches is filled inwith a first filling layer; ion implantation for forming said secondimpurity regions (4) into the sidewalls on both sides of each of saidplurality of second trenches (23) forming said second group of trenchesunder a condition wherein said first group of trenches is filled in witha second filling layer; implanting impurity ions of the same conductivetype as that of the already implanted impurities into the sidewalls onboth sides of the trenches (23) other than said trench (23) at theoutermost portion under the condition wherein the trench (23) at theoutermost portion, located at the outermost portion, from among saidplurality of first trenches (23) forming said first group of trenchesand said plurality of second trenches (23) forming said second group oftrenches is filled in with a third filling layer so as to increase theconcentration of the already implanted impurities so that said first orsecond impurity regions (3, 4) of the sidewalls of the trench (23) atthe outermost portion become regions of a comparatively lowconcentration.